Intel IXP2800 - page 21

Hardware Reference Manual 21
Contents
95 Order in which Data is Transmitted from TBUF....................................................................... .263
96 Mapping of TBUF Partitions to Transmit Protocol......... ...........................................................263
97 Number of Elements per TBUF Partition............. ..................................................................... 264
98 TBUF SPI-4 Control Definition.............................................................................. ....................266
99 TBUF CSIX Control Definition ..................................................................................................267
100 Transmit SPI-4 Control Word............................ ........................................................................268
101 Transmit CSIX Header............................ ..................................................................................269
102 Summary of RBUF and TBUF Operations........................... .....................................................274
103 SRB Definition by Clock Phase Number........................................... ........................................276
104 Data Deskew Functions ............................................................................................................ 281
105 Calendar Deskew Functions .....................................................................................................281
106 Flow Control Deskew Functions .................................................................................... ...........281
107 Data Training Sequence ........................................................................................................... 282
108 Flow Control Training Sequence ................................................................... ...........................282
109 Calendar Training Sequence .................................................................................................... 283
110 IXP2800 Network Processor Requires Data Training....................... ........................................284
111 Switch Fabric or SPI-4 Framer Requires Data Training .......................................................... .285
112 IXP2800 Network Processor Requires Flow Control Training ..................................................286
113 Switch Fabric Requires Flow Control Training............... ...........................................................286
114 SPI-4.2 Transmitter State Machine Transitions on 16-Bit Bus Transfers ................................. 314
115 Training Transmitter State Machine Transitions on 16-Bit Bus Transfers ................................ 315
116 CSIX-L1 Transmitter State Machine Transitions on CWord Boundaries ................................. .315
117 PCI Block FIFO Sizes ............................................................................................................... 322
118 Maximum Loading ................................................................... .................................................322
119 PCI Commands ................................................................ ........................................................322
120 PCI BAR Programmable Sizes ................................................................................................. 324
121 PCI BAR Sizes with PCI Host Initialization ............................................................................... 324
122 Legal Combinations of the Strap Pin Options............. ..............................................................330
123 Slave Interface Buffer Sizes .................................................... .................................................332
124 Doorbell Interrupt Registers.............. ........................................................................................337
125 IRQ Interrupt Options by Stepping.................................... ........................................................339
126 DMA Descriptor Format ............................................................................................................ 342
127 PCI Maximum Burst Size .......................................................................................................... 345
128 Command Bus Master Configuration Transactions ..................................................................347
129 Command Bus Master Address Space Map to PCI.............................................. ....................347
130 Byte Lane Alignment for 64-Bit PCI Data In (64 Bits PCI Little-Endian to Big-Endian
with Swap)................................. ...............................................................................................353
131 Byte Lane Alignment for 64-Bit PCI Data In (64 Bits PCI Big-Endian to Big-Endian
without Swap)................................ ...........................................................................................353
132 Byte Lane Alignment for 32-Bit PCI Data In (32 Bits PCI Little-Endian to Big-Endian
with Swap)................................. ...............................................................................................353
133 Byte Lane Alignment for 32-Bit PCI Data In (32 Bits PCI Big-Endian to Big-Endian
without Swap)................................ ...........................................................................................353
134 Byte Lane Alignment for 64-Bit PCI Data Out (Big-Endian to 64 Bits PCI Little
Endian with Swap)............................................................ ........................................................354
135 Byte Lane Alignment for 64-Bit PCI Data Out (Big-Endian to 64 Bits PCI Big-Endian
without Swap)................................ ...........................................................................................354
136 Byte Lane Alignment for 32-Bit PCI Data Out (Big-Endian to 32 Bits PCI Little
Endian with Swap)............................................................ ........................................................354
137 Byte Lane Alignment for 32-Bit PCI Data Out (Big-Endian to 32 Bits PCI Big-Endian
without Swap)................................ ...........................................................................................354