Hardware Reference Manual 107
Intel® IXP2800 Network Processor
Intel XScale® Core
3.8 Performance Monitoring
The Intel XScale® core hardware provides two 32-bit performance counters that allow two unique
events to be monitored simultaneously. In addition, the Intel XScale® core implements a 32-bit
clock counter that can be used in conjunction with the performance counters; its sole purpose is to
count the number of core clock cycles, which is useful in measuring total execution time.
The Intel XScale® core can monitor either occurrence events or duration events. When counting
occurrence events, a counter is incremented each time a specified event takes place and when
measuring duration, a counter counts the number of processor clocks that occur while a specified
condition is true. If any of the three counters overflow, an IRQ or FIQ will be generated if it’s
enabled. Each counter has its own interrupt enable. The counters continue to monitor events even
after an overflow occurs, until disabled by software. Refer to the Intel® IXP2400 and IXP2800
Network Processor Programmer’s Reference Manual for more detail.
Each of these counters can be programmed to monitor any one of various events.
To further augment performance monitoring, the Intel XScale® core clock counter can be used to
measure the executing time of an application. This information combined with a duration event can
feedback a percentage of time the event occurred with respect to overall execution time.
Each of the three counters and the performance monitoring control register are accessible through
Coprocessor 14 (CP14), registers 0-3. Access is allowed in privileged mode only.
The following are a few notes about controlling the performance monitoring mechanism:
•An interrupt will be reported when a counter’s overflow flag is set and its associated interrupt
enable bit is set in the PMNC register. The interrupt will remain asserted until software clears
the overflow flag by writing a one to the flag that is set. Note: the product specific interrupt
unit and the CPSR must have enabled the interrupt in order for software to receive it.
•The counters continue to record events even after they overflow.

3.8.1 Performance Monitoring Events

Table24 lists events that may be monitored by the PMU. Each of the Performance Monitor Count
registers (PMN0 and PMN1) can count any listed event. Software selects which event is counted
by each PMNx register by programming the evtCountx fields of the PMNC register.
Table 24. Performance Monitoring Events (Sheet 1 of 2)
Event Number
(evtCount0 or
evtCount1)
Event Definition
0x0 Instruction cache miss requires fetch from external memory.
0x1 Instruction cache cannot deliver an instruction. This could indicate an ICache miss or an
ITLB miss. This event will occur every cycle in which the condition is present.
0x2 Stall due to a data dependency. This event will occur every cycle in which the condition is
present.
0x3 Instruction TLB miss.
0x4 Data TLB miss.
0x5 Branch instruction executed, branch may or may not have changed program flow.
0x6 Branch mispredicted. (B and BL instructions only.)