Intel IXP2800 7.1.2.2 Scratchpad Interface, 7.1.2.3 Scratchpad Block Level Diagram

Hardware Reference Manual 229
Intel® IXP2800 Network Processor
SHaC — Unit Expansion
7.1.2.2 Scratchpad Interface
Note: The Scratchpad command and S_Push and S_Pull bus interfaces actually are shared with the Hash
Unit. Only one command, to either of those units, can be accepted per cycle.
The CSR and APB buses are described in detail in the following sections.
7.1.2.2.1 Command Interface
The Scratchpad accepts commands from the Command Bus and can accept one command every
cycle.
For Push/Pull reflector write and read commands, the command bus is rearranged before being sent
to the Scratchpad state machine to allow a single state (REFLECT_PP) to be used to handle both
commands.
7.1.2.2.2 Push/Pull Interface
The Scratchpad has the capability to interface to either one or two pairs of push/pull (PP) bus pairs.
The interface from the Scratchpad to the PP bus pair is through the Push/Pull Arbiters. Each PP bus
has a separate Push and Pull arbiter through which access to the Push bus and Pull bus,
respectively, is regulated. Refer to the SRAM Push Arbiter and SRAM Pull Arbiter chapters for
more information. When the Scratchpad is used in a chip that only utilizes one pair of PP buses, the
other interface is unused.
7.1.2.2.3 CSR Bus Interface
The CSR Bus provides fast write and standard read and write operations from the Scratchpad to the
CSRs in the CSR block.
7.1.2.2.4 Advanced Peripherals Bus Interface (APB)
The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture
(AMBA) hierarchy of buses that are optimized for minimal power consumption and reduced
design complexity.
Note: The SHaC Unit uses a modified APB interface in which the APB peripheral is required to generate
an acknowledge signal (APB_RDY_H) during read operations. This is done to indicate that valid
data is on the bus. The addition of the acknowledge signal is an enhancement added specifically for
the IXP2800 Network Processor architecture. (For more details refer to the ARM* AMBA
Specification 1.6.1.3.)
7.1.2.3 Scratchpad Block Level Diagram
Scratchpad Command Overview
This section describes the operations performed for each Scratchpad command. Command order is
preserved because all commands go through a single command inlet FIFO.
When a valid command is placed on the command bus, the control logic checks the instruction
field for the Scratchpad or CAP ID. The command, address, length, etc., are enqueued into the
Command Inlet FIFO. If the command requires pull data, signals are generated and immediately
sent to the Pull Arbiter. The command is pushed from the Inlet FIFO to the command pipe where it
is serviced according to the command type.