Intel IXP2800 Table 131. Byte Lane Alignment for 64-Bit PCI Data In (64 Bits PCI Big-Endian to Big-Endian, Table 133. Byte Lane Alignment for 32-Bit PCI Data In (32 Bits PCI Big-Endian to Big-Endian

Hardware Reference Manual 353
Intel® IXP2800 Network Processor
PCI Unit
--
Table 130. Byte Lane Alignment for 64-Bit PCI Data In (64 Bits PCI Little-Endian to Big-Endian
with Swap)
PCI Data IN[63:56] IN[55:48] IN[47:40] IN[39:32] IN[31:24] IN[23:16] IN[15:8] IN[7:0]
SRAM Data
OUT[7:0] OUT[15:8] OUT[23:16] OUT[31:24] OUT[7:0] OUT[15:8] OUT[23:16] OUT[31:24]
Longword1 (32 bits)
LW1 drive after LW0
Longword0 (32 bits)
LW0 drive first
DRAM Data OUT[39:32] OUT[47:40] OUT[55:48] OUT[63:56] OUT[7:0] OUT[15:8] OUT[23:16] OUT[31:24]
Table 131. Byte Lane Alignment for 64-Bit PCI Data In (64 Bits PCI Big-Endian to Big-Endian
without Swap)
PCI Data IN[39:32] IN[47:40] IN[55:48] IN[63:56] IN[7:0] IN[15:8] IN[23:16] IN[31:24]
SRAM Data OUT[7:0] OUT[15:8] OUT[23:16] OUT[31:24] OUT[7:0] OUT[15:8] OUT[23:16] OUT[31:24]
Longword1 (32 bits)
LW1 drive after LW0
Longword0 (32 bits)
LW0 drive first
DRAM Data OUT[39:32] OUT[47:40] OUT[55:48] OUT[63:56] OUT[7:0] OUT[15:8] OUT[23:16] OUT[31:24]
Table 132. Byte Lane Alignment for 32-Bit PCI Data In (32 Bits PCI Little-Endian to Big-Endian
with Swap)
PCI Add[2]=1 PCI Add[2]=0
Longword1 (32 bits)
LW1 drive after LW0
Longword0 ((32 bits)
LW0 drive first
PCI Data IN[31:24] IN[23:16] IN[15:8] IN[7:0] IN[31:24] IN[23:16] IN[15:8] IN[7:0]
SRAM Data OUT[7:0] OUT[15:8] OUT[23:16] OUT[31:24] OUT[7:0] OUT[15:8] OUT[23:16] OUT[31:24]
Longword1 (32 bits)
LW1 drive after LW0
Longword0 ((32 bits)
LW0 drive first
DRAM Data OUT[39:32] OUT[47:40] OUT[55:48] OUT[63:56] OUT[7:0] OUT[15:8] OUT[23:16] OUT[31:24]
Table 133. Byte Lane Alignment for 32-Bit PCI Data In (32 Bits PCI Big-Endian to Big-Endian
without Swap)
PCI Add[2]=1 PCI Add[2]=0
Longword1 (32 bits)
LW1 drive after LW0
Longword0 ((32 bits)
LW0 drive first
PCI Data IN[7:0] IN[15:8] IN[23:16] IN[31:24] IN[7:0] IN[15:8] IN[23:16] IN[31:24]
SRAM Data OUT[7:0] OUT[15:8] OUT[23:16] OUT[31:24] OUT[7:0] OUT[15:8] OUT[23:16] OUT[31:24]
Longword1 (32 bits)
LW1 drive after LW0
Longword0 ((32 bits)
LW0 drive first
direct map
pci to dram IN[7:0] IN[15:8] IN[23:16] IN[31:24] IN[7:0] IN[15:8] IN[23:16] IN[31:24]
DRAM Data OUT[39:32] OUT[47:40] OUT[55:48] OUT[63:56] OUT[7:0] OUT[15:8] OUT[23:16] OUT[31:24]