Hardware Reference Manual 305
Intel® IXP2800 Network Processor
Media and Switch Fabric Interface
The network processor supports a variation of the standard CSIX-L1 vertical parity. Instead of a
single vertical XOR for the calculation of the vertical parity, the network processor can be
configured to calculate as DIP-16 code, as documented within the SPI-4.2 specification. If
horizontal parity is not enabled for the interface, the use of the DIP-16 code is recommended to
provide for better error coverage than that provided by a vertical parity.
8.9.4.2.2 Support for Dual Chip, Full-Duplex Operation
A dual-chip configuration of network processors consisting of an ingress and egress network
processor, can present a full-duplex interface to a fabric interface chip, consistent with the
expectations of the CSIX-L1 protocol. A flow control interface is supported between the ingress
and egress chips to forward necessary flow control information from the egress network processor
to the ingress network processor. Additional information can be transferred between the ingress
and egress network processors through the PCI bus.
The flow control interface consists of a data transfer signal group, a serial signal for conveying the
state of the CSIX-L1 “ready bits” (TXCSRB, RXCSRB), and a backpressure signal (TXCFC,
RXCFC) to avoid overrunning the receiver in the ingress network processor. (The orientation of the
signal names is consistent with the egress network processor, receiving CFrames from the fabric,
and forwarding flow control information out through the transmit flow control pins.) The data
transfer signal group consists of:
•Four data signals (TXCDAT[0..3], RXCDAT[0..3])
•A clock (TXCCLK, RXCCLK)
•A start-of-frame signal (TXCSOF, RXCSOF)
•A horizontal-parity signal (TXCPAR, RXCPAR)
The network processor receiver forwards Flow Control CFrames from the fabric in a cut-through
fashion over the flow control interface. The flow control interface has one-fourth of the bandwidth
of the network processor fabric data interface. The Crdy bit in the base header of the CSIX-L1
protocol (link-level flow control) prevents overflowing of the FIFO for transmitting out the flow
control interface from the egress network processor. The fabric can implement a rate limit on the
transmission of Flow Control CFrames to the egress network processor, consistent with the
bandwidth available on the flow control interface. With a rate limit, the fabric can detect
congestion of Flow Control CFrames earlier, instead of waiting for the assertion of cascaded
backpressure signals.
The CRdy and DRdy bits of CFrames sent across the flow control interface are set to 0 on
transmission and ignored upon reception at the ingress network processor. If no CFrames are
available to send from the egress network processor to the ingress network processor, an alternating
sequence of Idle CFrames and Dead Cycles is sent from the egress to the ingress network
processor, consistent with the CSIX-L1 protocol.
The state of the CRdy and DRdy bits sent to the egress network processor by the fabric and the
state of the CRdy and DRdy bits that should be sent to the fabric by the ingress network processor,
reflecting the state of the egress network processor buffering, are sent through the TXCSRB signal
and received through the RXCSRB signal. A new set of bits are conveyed every 10 clock edges or
five clock cycles, of the interface. A de-assertion of a “ready bit” is forwarded immediately upon
processing the “ready bit”. An assertion of a “ready bit” is forwarded only after all of the horizontal
parities and the vertical parity of the CFrame are checked. A configuration of ingress and egress
network processors is expected to respond to the de-assertion of a CRdy or DRdy bit within 32
clock cycles (RCLK), consistent with the formulation described for CSIX-L1.