Hardware Reference Manual 7
Contents
3.11.5 I/O Transaction............... ..................................................................................... 130
3.11.6 Hash Access....................................................................... .................................130
3.11.7 Gasket Local CSR.... ...........................................................................................131
3.11.8 Interrupt ............................................................................................................... 132
3.12 Intel XScale® Core Peripheral Interface........................................................................... 134
3.12.1 XPI Overview............................................ ...........................................................134
3.12.1.1 Data Transfers....................................... ..............................................135
3.12.1.2 Data Alignment......... ...........................................................................135
3.12.1.3 Address Spaces for XPI Internal Devices............................................ 136
3.12.2 UART Overview..................................... ..............................................................137
3.12.3 UART Operation.......... ........................................................................................138
3.12.3.1 UART FIFO OPERATION.................................................................... 138
3.12.3.1.1 UART FIFO Interrupt Mode Operation –
Receiver Interrupt...................... ..............................................138
3.12.3.1.2 FIFO Polled Mode Operation......................................... ....139
3.12.4 Baud Rate Generator........................................................................................... 139
3.12.5 General Purpose I/O (GPIO) ............................................................................... 140
3.12.6 Timers.......................................................................... ........................................141
3.12.6.1 Timer Operation........................................................................ ...........141
3.12.7 Slowport Unit ....................................................................................................... 142
3.12.7.1 PROM Device Support......................................................................... 143
3.12.7.2 Microprocessor Interface Support for the Framer............................ ....143
3.12.7.3 Slowport Unit Interfaces....................................................................... 144
3.12.7.4 Address Space..................................................................................... 145
3.12.7.5 Slowport Interfacing Topology........ .....................................................145
3.12.7.6 Slowport 8-Bit Device Bus Protocols ...................................................146
3.12.7.6.1 Mode 0 Single Write Transfer for Fixed-Timed Device......147
3.12.7.6.2 Mode 0 Single Write Transfer for Self-Timing Device........ 148
3.12.7.6.3 Mode 0 Single Read Transfer for Fixed-Timed Device......149
3.12.7.6.4 Single Read Transfer for a Self-Timing Device..................150
3.12.7.7 SONET/SDH Microprocessor Access Support................... .................150
3.12.7.7.1 Mode 1: 16-Bit Microprocessor Interface Support with
16-Bit Address Lines................................................................151
3.12.7.7.2 Mode 2: Interface with 8 Data Bits and 11 Address Bits.... 155
3.12.7.7.3 Mode 3: Support for the Intel and AMCC* 2488 Mbps
SONET/SDH Microprocessor Interface.................. .................157
4Microengines........... .................................................................................................................. 167
4.1 Overview................................................................................ ...........................................167
4.1.1 Control Store........................................................................................................ 169
4.1.2 Contexts.............................................................................................. .................169
4.1.3 Datapath Registers................................................ ..............................................171
4.1.3.1 General-Purpose Registers (GPRs) ....................................................171
4.1.3.2 Transfer Registers ...............................................................................171
4.1.3.3 Next Neighbor Registers...................................................................... 172
4.1.3.4 Local Memory. .....................................................................................172
4.1.4 Addressing Modes.......................................... .....................................................173
4.1.4.1 Context-Relative Addressing Mode .....................................................173
4.1.4.2 Absolute Addressing Mode................................................................. .174
4.1.4.3 Indexed Addressing Mode.............................. .....................................174
4.2 Local CSRs ......................................................................................................... ..............174
4.3 Execution Datapath ..................... .....................................................................................174