Hardware Reference Manual 79
Intel® IXP2800 Network Processor
Intel XScale® Core
Intel XScale® Core 3
This section contains information describing the Intel XScale® core, Intel XScale® core gasket, and
Intel XScale® core Peripherals (XPI).
For additional information about the Intel XScale® architecture refer to the Intel XScale® Core
Developers Manual available on Intel’s Developers web site (http://www.developer.intel.com).

3.1 Introduction

The Intel XScale® core is an ARM* V5TE compliant microprocessor. It has been designed for high
performance and low-power; leading the industry in mW/MIPs. The Intel XScale® core
incorporates an extensive list of architecture features that allows it to achieve high performance.
Many of the architectural features added to the Intel XScale® core help hide memory latency that
often is a serious impediment to high performance processors.
This includes:
The ability to continue instruction execution even while the data cache is retrieving data from
external memory.
A write buffer.
Write-back caching.
Various data cache allocation policies that can be configured different for each application.
Cache locking.
All these features improve the efficiency of the memory bus external to the core.
ARM* Version 5 (V5) Architecture added floating point instructions to ARM* Version 4. The Intel
XScale® core implements the integer instruction set architecture of ARM* V5, but does not
provide hardware support of the floating point instructions.
The Intel XScale® core provides the Thumb instruction set (ARM* V5T) and the ARM* V5E DSP
extensions.