Intel IXP2800 3.11.5 I/O Transaction, 3.11.6 Hash Access

130 Hardware Reference Manual
Intel® IXP2800 Network Processor
Intel XScale® Core
3.11.5 I/O Transaction
The Intel XScale® core can request an I/O transaction by asserting xsoCBI_IO concurrently with
xsoCBI_Req. The value of xsoCBI_IO is undefined when xsoCBI_Req is not asserted. When the
gasket sees an I/O request with xsoCBI_IO asserted, it will raise xsiCBR_Ack but will not
acknowledge future requests until the IO transaction is complete. The gasket will check if all of the
command FIFOs and write data FIFOs are empty or not. It will also check if the command counters
(SRAM and DRAM) are equal to 0. All of these checks are to guarantee that:
•Writes are issued to the target, and targets have pulled the data.
•Pending reads have their data all back to the gasket.
When the gasket sees that all of the conditions are satisfied, it will assert xsiCBR_SynchDone to
the Intel XScale® core. XsiCBR_SynchDone is one cycle long and does not need to coincide with
xsiCBR_DataValid.
3.11.6 Hash Access
Hash accesses are accomplished by the gasket Local_CSR accesses from the Intel XScale® core.
There are two sets of registers in the gasket that are involved in Hash accesses.
•Four 32-bit XG_GCSR_Hash[3:0] registers for holding the data to be hashed and index
returned as well.
•A XG_GCSR_CTR0(valid) register to hold the status of the Hash Access.
The procedure for the Intel XScale® core to setup a Hash access is as follows.
1. The Intel XScale® core writes data to XG_GCSR_Hash by Local_CSR access, using address
[X:yy:zz]. X selects Hash register set, yy selects hash_48, hash_64, or hash_128 mode, and zz
selects one of four Hash_Data registers.
2. The data write order is 3-2-1-0 (for hash_128) and 1-0 (for hash_48 or hash_64). When the
data write to Hash_Data[0] is performed, it triggers the Hash request to go out on the CPP bus.
At the same time, XG_GCSR_Hash(valid) is cleared by hardware.
3. The Intel XScale® core starts to poll Hash_Result_Valid periodically by Local_CSR read.
4. After a period of time, the Hash_Result is returned to XG_GCSR_Hash, and
XG_GCSR_CTR0(valid) is set to indicate that Hash_Result is ready to be retrieved.
5. The Intel XScale® core issues a Local_CSR read to read back the Hash_Result.
Note: Each Hash command requests only one index returned.
The Hash CSR is in the gasket local CSR space. See Section3.11.7.