326 Hardware Reference Manual
Intel® IXP2800 Network Processor
PCI Unit
9.2.5 PCI Target Cycles
The following PCI transactions are not supported by the PCI Unit as a target:
•IO read or write
•Type 1 configuration read or write
•Special cycle
•IACK cycle
•PCI Lock cycle
•Multi-function devices
•Dual Address cycle
9.2.5.1 PCI Accesses to CSR
A PCI access to a CSR occurs if the PCI address matches the CSR base address register
(PCI_CSR_BAR).The PCI Bus will be disconnected after the first data-phase if the data is more
than one data phase. For 64-bit CSR accesses, the PCI Unit will not assert PCI_ACK64_L on the
PCI bus.
9.2.5.2 PCI Accesses to DRAM
A PCI access to DRAM occurs if the PCI address matches the DRAM base address register
(PCI_DRAM_BAR).
9.2.5.3 PCI Accesses to SRAM
A PCI access to SRAM occurs if the PCI address matches the SRAM base address register
(PCI_SRAM_BAR). The SRAM is organized as three distinct channel and the address is not
contiguous. The PCI_SRAM_BAR programmed window size will be used as the total memory
space. The upper two bits of the address will be used as channel number in addressing the
particular channel and the remaining address bits will be used as the memory address.
9.2.5.4 Target Write Accesses from the PCI Bus
A PCI write occurs if the PCI address matches one of the base address registers and the PCI
command is either a Memory Write or Memory Write and Invalidate. The core will store up to four
write addresses into the target address FIFO along with the BAR IDs of the transaction. The write
data will be stored into the target write FIFO.When either the address FIFO or data FIFO is full, a
retry is forced on the PCI Bus in response to write accesses.
The FIFO data is forwarded to an internal slave buffer before being written into SRAM or DRAM.
If the FIFO fills during the write, the address is crossing the 64-byte address boundary, or in the
case of the command being a burst to the CSR space, the PCI unit signals target disconnect to the
PCI master.