Intel IXP2800 5.10.1 Commands, 5.10.2 DRAM Write

Hardware Reference Manual 199

Intel® IXP2800 Network Processor

DRAM

5.10.1 Commands

When a valid command is placed on the command bus, the control logic checks to see if the

address matches the channel’s address range, based on interleaving as described in Section5.5.

The command, address, length, etc. are enqueued into the command Inlet FIFO.

If the command Inlet FIFO becomes full, the channel sends a signal to the command arbiter, which

will prevent it from sending further DRAM commands. The full signal must be asserted while there

is still enough room in the FIFOs to hold the worst case number of in-flight commands.

5.10.2 DRAM Write

When a write (or RBUF_RD, which does a DRAM write) command is at the head of the Command

Inlet FIFO, it is moved to the proper Bank CMD FIFO, and the Pull_ID is sent to the Pull arbiter.

This can only be done if there is room for the command in the Bank’s CMD FIFO and for the pull

data in the Bank’s Pull Data FIFO (which must take into account all pull data in flight). If there is

not enough room in the Bank’s CMD FIFO or the Bank’s Pull Data FIFO, the write command waits

at the head of the Command Inlet FIFO. When the Pull_ID is sent to the Pull Arbiter, the Bank

number is put into the PP (Pull in Progress) FIFO; this allows the channel to sort the Pull Data into

the proper Bank Pull Data FIFO when it arrives.

The source of the Pull Data can be either RBUF, PCI, Microengine, or the Intel XScale® core, and

is specified in the Pull_ID. When the source is RBUF or PCI, data will be supplied to the Pull Data

FIFO, at 64 bits per cycle. When the source is Microengine or the Intel XScale® core, data will be

supplied at 32 bits per cycle, justified to the low 32 bits of Pull Data. The Pull Arbiter must merge

and pack data as required. In addition, the data must be aligned according to the start address,

which has longword resolution; this is done in Pre_RMC.

The Length field of the command at the head of the Bank CMD FIFO is compared to the number of

64-bit words in the Bank Pull_Data FIFO. When the number of 64-bit words in Pull_Data FIFO is

greater or equal to the length, the write arbitrates for the RMC. When it wins arbitration, it sends

the address and command to RMC, which requests the write data from Pull_Data FIFO at the

proper time to send it to the RDRAMs.

Note: The Microengine is signaled when the last data is pulled.

Masked writes (write of less than eight bytes) are done as either Read-Modify-Writes when ECC is

enabled, or as Rambus*-masked writes (using COLM packets), when ECC is not enabled. In both

cases, the masked write will modify seven or fewer bytes because the command bus limits a

masked write to a ref_count of 1.

If a RMW is used, no commands from that Bank’s CMD FIFO are started between the read and the

write; other Bank commands can be done during that time.