Intel IXP2800 SRAM Interface 6

Hardware Reference Manual 207
Intel® IXP2800 Network Processor
SRAM Interface
SRAM Interface 6
6.1 Overview
The IXP2800 Network Processor contains four independent SRAM controllers. SRAM controllers
support pipelined QDR synchronous static RAM (SRAM) and a coprocessor that adheres to QDR
signaling. Any or all controllers can be left unpopulated if the application does not need them.
Reads and writes to SRAM are generated by Microengines (MEs), the Intel XScale® core, and PCI
Bus masters. They are connected to the controllers through Command Buses and Push and Pull
Buses. Each of the SRAM controllers takes commands from the command bus and enqueues them.
The commands are de-queued according to priority, and successive accesses to the SRAMs are
performed.
Each SRAM controller receives commands using two Command Buses, one of which may be tied
off as inactive, depending on the chip implementation. The SRAM Controller can enqueue a
command from each Command Bus in each cycle. Data movement between the SRAM controllers
and the Microengines is through the S_Push bus and S_Pull bus.
The overall structure of the SRAM controllers is shown in Figure 74.