Manuals / Omega Engineering / Computer Equipment / Computer Hardware

Omega Engineering manual Self-Calibration of the PCI-DAS1200, RefPGA, Variable Gain

Models: PCI-DAS1200

1 43

Download 43 pages 61.69 Kb

Page 20

6.0 Self-Calibration of the PCI-DAS1200

6.0 Self-Calibration of the PCI-DAS1200

The PCI-DAS1200 is shipped fully-calibrated from the factory with cal coefficients stored in nvRAM. When using Universal Library at run time, these calibration factors are loaded into system memory and are automatically retrieved each time a different DAC/ADC range is specified. The user has the option to recalibrate with respect to the factory-measured voltage standards at any time by simply selecting the "Calibrate" option in InstaCal. Full calibration typically requires less than two minutes and requires no user intervention.

6.1 CALIBRATION CONFIGURATION

The PCI-DAS1200 provides self-calibration of the analog source and measurment systems thereby eliminating the need for external equipment and user adjustments. All adjustments are made via 8-bit calibration DACs or 7-bit digital potentiometers referenced to an on-board factory calibrated standard. Calibration factors are stored on the serial nvRAM..

A variety of methods are used to calibrate the different elements on the board. The analog front-end has several knobs to turn. Offset calibration is performed in the instrumentation amplifier gain stage. Front-end gain adjustment is performed via a variable attenuator/gain stage.

The analog output circuits are calibrated for both gain and offset. Offset adjustments for the analog output are made in the output buffer section. The tuning range of this adjustment allows for max DAC and output buffer offsets. Gain calibration of the analog outputs are performed via DAC reference adjustments.

Figure 1 below is a block diagram of the analog front-end calibration system:

Cal

RefPGA






							Offset Adj
8						O f f s e t
8		T r i m D a c				O f f s e t
		T r i m D a c
		(Coarse)
		T r i m D a c
		T r i m D a c
		(Fi ne)

Variable Gain

ADC

7

Digital Offset Pot

Figure 1

17

Image 20

Omega Engineering manual Self-Calibration of the PCI-DAS1200, RefPGA, Variable Gain, Calibration Configuration

Contents

PCI-DAS1200 Users Guide3.1 CONNECTOR PIN DIAGRAM 4.2 WIRING CONFIGURATIONS6.1 CALIBRATION CONFIGURATION 3.0 HARDWARE CONNECTIONSTable of Contents 1.0 INTRODUCTION ORFN3&,$LDJUDP6PCI BUS 5V, 32-BIT, 33MHZ 3&,%ORFN$LDJUDP6-5LOCAL BUS 2.1.2 Launching InstaCal 2.0 INSTALLATION2.1.1 Install the InstaCAL software 2.1.3 Using InstaCal 2.1.4 Testing the Installation2.2.1 Install the InstaCal software 2.2.3 Using InstaCal2.2.2 Launching InstaCal 2.2 DOS AND/OR WINDOWS2.2.4 TESTING THE INSTALLATION 3.0 HARDWARE CONNECTIONS A nalog Input C h 0 Low / 8 H ighA nalog Input C h 1 Low / 9 H igh A nalog Input C h 2 Low / 10 H igh4.0 ANALOG CONNECTIONS 4.1.1 Single-Ended and Differential InputsSingle-Ended Inputs Single-Ended InputDifferential Inputs Differential InputS in gle -ended input w ith C om m on M ode Voltage D iffe rential Inp ut4.1.2 System Grounds and Isolation Which system do you have?Systems with Common Grounds Systems with Common Mode ground offset VoltagesPCI-DAS1200 and signal source already have isolated grounds Input ConfigurationSmall Common Mode Voltages Large Common Mode Voltages4.2.2 Common Ground / Differential Inputs A /D BoardA /D Board A /D Board A /D Board4.2.3 Common Mode Voltage +/-10V / Single-Ended Inputs 4.2.4 Common Mode Voltage +/-10V / Differential InputsA/D Board A /D BoardA /D Board 4.2.6 Isolated Grounds / Single-Ended Inputs5.0 Programming & Applications 6.0 Self-Calibration of the PCI-DAS1200 6.1 CALIBRATION CONFIGURATIONRefPGA Variable GainD A C A n alo g O u tR e f G ain A d j O ffset A dj7.0 PCI-DAS1200 Register Description 7.2 BADR07.3 BADR1 7.3.1 INTERRUPT / ADC FIFO REGISTERINTE EOAIEEOACL INTCLEOBI ADHFIADNEI ADNE7.3.3 TRIGGER CONTROL/STATUS REGISTER ResolutionUNIBIP Input RangeTS10 TGENSource C0SRCC0SRC XTRIGINDXGT PRTRG7.3.4 CALIBRATION REGISTER DAC ChannelCal Function CSRC2CALEN 7.3.5 DAC CONTROL/STATUS REGISTER Does not apply to PCI-DAS1200/JRDACEN MODE DACnR10 with SEL8800 and SEL7376 bits7.4.2 ADC FIFO CLEAR REGISTER 7.4 BADR27.4.1 ADC DATA REGISTER 7.5 BADR3 7.5.1 ADC PACER CLOCK DATA AND CONTROL REGISTERSDevice Counter #DIO PORT A DATA ADC 8254 CONTROL REGISTER7.5.2 DIGITAL I/O DATA AND CONTROL REGISTERS DIO PORT B DATA DIO PORT C DATADIO CONTROL REGISTER BADR3 +7.5.3 INDEX and USER COUNTER DATA AND CONTROL REGISTERS 8254BCOUNTER 0 DATA-ADC8254B COUNTER 1 DATA - USER COUNTER #5 8254B COUNTER 2 DATA - USER COUNTER #68254B CONTROL REGISTER BADR3 +7.6.2 DAC1 DATA REGISTER 7.6 BADR47.6.1 DAC0 DATA REGISTER 8.0 Electrical Specifications ANALOG OUTPUT Does not apply to PCI-DAS1200/JR Resolution Offset error Gain error Differential nonlinearityConfiguration Number of channels Output High Output Low Input High Input Low Power-up / reset state Interrupts Interrupt enableConfiguration Counter type82C54 82C54AOTHER SPECIFICATIONS Power consumptionIcc Operating A/D converting to FIFO 0.8 A typical, 1.0 A maxFOR YOUR NOTES EC Declaration of Conformity