
1.0 INTRODUCTION
The
Even the connector has changed. New, denser connectors allow up to 100 signal lines where 37 was once the standard.
The
These products are supported by our Universal Library programming library. As an owner, you are entitled to the latest revision of the manual and software. Just call with your current revision numbers handy, and request an update be sent to you.
Gain and Offset Autocal
Gain and Offset Autocal
Burst/Scan ![]()
Mux
&
Gain
Analog In
16CH S.E.![]()
8CH DIFF.
Gains = 1, 2, 4, 8
ADC |
| |
Pacer |
| |
CTR 2 | r o l | |
CTR 1 | n t | |
Co | ||
| ||
Sample |
| |
Counter |
| |
CTR0 |
|
Start EOC
EXT PCR
10 MHz![]()
1024 x 12
FIFO
I N T
Burst/Scan
CONTROLLER
FPGA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| VDAC 0 | ||
DAC |
| DAC0 |
|
|
|
|
| |
|
|
|
|
|
| |||
|
|
|
|
|
|
| ||
Data |
|
|
|
|
|
|
| |
Control |
|
|
|
| VDAC 1 | |||
|
|
|
|
|
| |||
|
|
| DAC1 |
|
|
|
|
|
|
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
INT |
Scan
ADC
&
DAC
ControlPacer
BurstLogic
Control
XTRIG
Trigger
Control
Decode/Status Int |
| INT |
| ||
|
| |
Ctl |
|
|
Bus
Time Base
CLK2![]()
GATE2![]()
OUT2![]()
CLK1![]()
GATE1![]()
OUT1![]()
INT![]()
XTRIG![]()
![]()
10MHz
CTR2 |
|
| ||
CTR1 | o l |
| ||
ADC | o n t r |
| ||
Index | C |
| ||
|
| |||
Counter |
|
| ||
User |
|
| ||
CTR 0 |
|
| ||
|
|
| GATE | |
|
|
| ||
|
|
| CLK | |
|
|
| ||
|
|
| OUT | |
|
|
| ||
Timing
%ORFN3&,'$'LDJUDP6
|
| Digital I/O |
|
|
|
|
|
|
|
| |||
PA (7:0) |
| Port A |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||
|
|
| l |
|
|
|
| Boot |
|
|
| BADR1 | |
|
|
| o |
|
|
|
| EEPROM |
| PCI | BADR2 | ||
PB (7:0) |
| Port B | t r |
|
|
|
|
|
| CONTROLLER | BADR3 | ||
|
|
| n |
|
|
|
|
|
| BADR4 | |||
|
|
| o |
|
|
|
|
|
|
|
| ||
|
|
| C |
|
|
|
|
|
|
|
| Interrupt | |
PC (7:0) |
| Port C |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
LOCAL BUS
PCI BUS (5V, 32-BIT, 33MHZ)
1