COUNTER SECTION

 

 

 

Counter type

82C54

 

Configuration

Two 82C54 devices. 3 down counters per 82C54, 16 bits each

 

 

82C54A:

 

 

 

Counter 0 - ADC residual sample counter.

 

 

Source:

ADC Clock.

 

 

Gate:

Internal programmable source.

 

 

Output:

End-of-Acquisition interrupt.

 

 

Counter 1 - ADC Pacer Lower Divider

 

 

Source:

10 MHz oscillator

 

 

Gate:

Tied to Counter 2 gate, programmable source.

 

 

Output:

Chained to Counter 2 Clock.

 

 

Counter 2 - ADC Pacer Upper Divider

 

 

Source:

Counter 1 Output.

 

 

Gate:

Tied to Counter 1 gate, programmable source.

 

 

Output:

ADC Pacer clock (if software selected), available at user

 

 

 

connector.

 

 

82C54B:

 

 

 

Counter 0 - Pretrigger Mode

 

 

Source:

ADC Clock.

 

 

Gate:

External trigger

 

 

Output:

End-of-Acquisition interrupt.

 

 

Counter 0 - User Counter 4 (when in non-Pretrigger Mode)

 

 

Source:

User input at 100-pin connector (CLK4) or internal

 

 

 

10 MHz (software selectable)

 

 

Gate:

User input at 100-pin connector (GATE4).

 

 

Output:

Available at 100-pin connector (OUT4).

 

 

Counter 1 - User Counter 5

 

 

Source:

User input at 100-pin connector (CLK5).

 

 

Gate:

User input at 100-pin connector (GATE5).

 

 

Output:

Available at 100-pin connector (OUT5).

 

 

Counter 2 - User Counter 6

 

 

Source:

User input at 100-pin connector (CLK6).

 

 

Gate:

User input at 100-pin connector (GATE6).

 

 

Output:

Available at 100-pin connector (OUT6).

Clock input frequency

 

10 MHz max

 

High pulse width (clock input)

30 ns min

 

Low pulse width (clock input)

50 ns min

 

Gate width high

 

50 ns min

 

Gate width low

 

50 ns min

 

Input low voltage

 

0.8 V max

 

Input high voltage

 

2.0 V min

 

Output low voltage

 

0.4 V max

 

Output high voltage

 

3.0 V min

 

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Image 39
Omega Engineering PCI-DAS1200 manual Counter Section, 82C54A