BADR3 + Ah, 8254B Control Register | Omega Engineering PCI-DAS1200

8254B COUNTER 1 DATA - USER COUNTER #5

BADR3 + 9

READ/WRITE

7	6	5	4	2	3	1	0

D7	D6	D5	D4	D3	D2	D1	D0

The clock, gate and output lines of Counter 1 are available to the user at the 100-pin connector as User Counter 5. The Counter 1 clock source is always external and must be provided by the user. The buffered version of the inter- nal 10-MHz clock available at the user connector may be used as the clock source.

8254B COUNTER 2 DATA - USER COUNTER #6

BADR3 + Ah

READ/WRITE

7	6	5	4	2	3	1	0

D7	D6	D5	D4	D3	D2	D1	D0

The clock, gate and output lines of Counter 2 are available to the user at the 100-pin connector as User Counter 6. The Counter 2 clock source is always external and must be provided by the user. The buffered version of the inter- nal 10-MHz clock available at the user connector may be used as the clock source.

8254B CONTROL REGISTER

BADR3 + Bh

WRITE ONLY

7	6	5	4	2	3	1	0

D7	D6	D5	D4	D3	D2	D1	D0

The control register is used to set the operating Modes of 8254B Counters 0,1 & 2. A counter is configured by writing the correct Mode information to the Control Register, then the proper count data must be written to the specific Counter Register.

The Counters on the 8254 are 16-bit devices. Since the interface to the 8254 is only 8-bits wide, Count data is written to the Counter Register as two successive bytes. First the low byte is written, then the high byte. The Control

Register is 8-bits wide. Further information can be obtained on the 8254 data sheet, available from Intel or Harris.

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Image 35

Omega Engineering PCI-DAS1200 manual 8254B Counter 1 Data User Counter #5, 8254B Counter 2 Data User Counter #6, BADR3 + Ah

Contents

Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Windows 95, 98 & NT Installation Using InstaCal DOS AND/OR Windows Testing the Installation Hardware Connections Connector PIN Diagram Analog Connections Differential Input Which system do you have? System Grounds and Isolation Systems with Common Grounds Systems with Common Mode ground offset Voltages PCI-DAS1200 and signal source already have isolated grounds Wiring ConfigurationsSmall Common Mode Voltages Large Common Mode Voltages Common Ground / Single-Ended Inputs Common Mode Voltage +/-10V Common Mode Voltage +/-10V / Single-Ended Inputs Board Programming Languages Programming & Applications Self-Calibration of the PCI-DAS1200 Alo g O u t Region Function Operations BADR0BADR1 Interrupt / ADC Fifo Register Intcl InteEoaie Eoacl ADC Channel MUX and Control Register Pacer Source Input Range Input Gain Measurement ResolutionEOC Trigger CONTROL/STATUS Register Tgen TS10 Xtrig Fifo Mode Sample CTRARM C0SRC Cal Source Calibration RegisterDAC Channel Cal Function DACnR10 Dacen ModeCalen SDI ADC Fifo Clear Register BADR2ADC Data Register BADR2 + BADR3 + BADR3ADC Pacer Clock Data and Control Registers 8254A Counter 0 Data ADC Post Trigger Conversion Counter Digital I/O Data and Control Registers 8254A Counter 2 Data ADC Pacer Divider UpperBase + ADC 8254 Control Register DIO Control Register DIO Port B DataDIO Port C Data Or User Index and User Counter Data and Control Registers 8254BCounter DATA-ADC PRE-TRIGGER Index Counter 8254B Control Register 8254B Counter 1 Data User Counter #58254B Counter 2 Data User Counter #6 BADR3 + Ah 2 DAC1 Data Register BADR41 DAC0 Data Register Analog Input Section Electrical Specifications Parallel Digital Input / Output Analog Output 82C54A Counter Section Environmental Other SpecificationsPower consumption For Your Notes EC Declaration of Conformity