Omega Engineering PCI-DAS1200 INDEX and USER COUNTER DATA AND CONTROL REGISTERS, 8254B, Counter

D4	D3	D1	D0	PORT A	PORT C	PORT B	PORT C
					UPPER		LOWER
0	0	0	0	OUT	OUT	OUT	OUT
0	0	0	1	OUT	OUT	OUT	IN
0	0	1	0	OUT	OUT	IN	OUT
0	0	1	1	OUT	OUT	IN	IN
0	1	0	0	OUT	IN	OUT	OUT
0	1	0	1	OUT	IN	OUT	IN
0	1	1	0	OUT	IN	IN	OUT
0	1	1	1	OUT	IN	IN	IN
1	0	0	0	IN	OUT	OUT	OUT
1	0	0	1	IN	OUT	OUT	IN
1	0	1	0	IN	OUT	IN	OUT
1	0	1	1	IN	OUT	IN	IN
1	1	0	0	IN	IN	OUT	OUT
1	1	0	1	IN	IN	OUT	IN
1	1	1	0	IN	IN	IN	OUT
1	1	1	1	IN	IN	IN	IN

7.5.3 INDEX and USER COUNTER DATA AND CONTROL REGISTERS

8254B	COUNTER		0 DATA—ADC		PRE-TRIGGER		INDEX	COUNTER	(or USER
COUNTER #4)
BADR3 + 8
READ/WRITE
7		6	5	4		2	3	1	0
D7		D6	D5	D4		D3	D2	D1	D0

Counter 0 of the 8254B device is a shared resource on the PCI-DAS1200. When not in ADC pre-trigger mode, the clock, gate and output lines of Counter 0 are available to the user at the 100-pin connector as User Counter 4. The Counter 0 clock source is SW selectable via the C0SRC bit in BADR1+4.

When in ADC Pre-trigger mode, this counter is used as the ADC Pre-Trigger index counter. This counter serves to mark the boundary between pre- and post-trigger samples when the ADC is operating in Pre-Trigger Mode. The External ADC Trigger flip flop gates Counter 0 on; the ADC FIFO Half-Full signal gates it off. Knowing the desired number of post-trigger samples, software can then calculate how may 1/2 FIFO data packets need to be collected and what corresponding residual sample count needs to be written to BADR3 + 0.

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