Omega Engineering PCI-DAS1200 manual BADR0, BADR1, Interrupt / ADC Fifo Register

7.0 PCI-DAS1200 Register Description

7.1 REGISTER OVERVIEW

PCI-DAS1200 operation registers are mapped into I/O address space. Unlike ISA bus designs, this board has several base addresses, each corresponding to a reserved block of addresses in I/O space. As we mention in our programming chapter, we highly recommend customers use the Universal Library package. Direct register level programming should be attempted only by extremely experienced register level programmers.

Of six Base Address Regions (BADR) available in the PCI 2.1 specification, five are implemented in this design and are summarized as follows:

I/O Region	Function	Operations
BADR0	PCI Controller Operation Registers	32-Bit DWORD
BADR1	General Control/Status Registers	16-Bit WORD
BADR2	ADC Data, FIFO Clear Registers	16-Bit WORD
BADR3	Pacer, Counter/Timer and DIO Registers	8-Bit BYTE
BADR4	DAC Data Registers (not applicable for (JR)	16-Bit WORD

BADRn will likely be different on different machines. Assigned by the PCI BIOS, these Base Address values cannot be guaranteed to be the same even on subsequent power-on cycles of the same machine. All software must interro- gate BADR0 at run-time with a READ_CONFIGURATION_WORD instruction to determine the BADRn values. Please see the "1997 AMCC S5933 PCI Controller Data Book” for more information.

7.2 BADR0

BADR0 is reserved for the AMCC S5933 PCI Controller operations. There is no reason to access this region of I/O space for most PCI-DAS1200 users. The installation procedures and Universal Library access all required informa- tion in this area. Unless you are writing direct register level software for the PCI-DAS1200, you will not need to be concerned with BADR0 address.

7.3 BADR1

The I/O region defined by BADR1 contains 5 control and status registers for ADC, DAC, interrupt and Autocal

operations. This region supports 16-bit WORD operations.

7.3.1 INTERRUPT / ADC FIFO REGISTER

BADR1+ 0: Interrupt Control, ADC status. A read/write register.

WRITE

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
-	-	ADFLCL	-	-	-	-	-	INTCL	EOACL	-	EOAIE	-	INTE	INT1	INT0

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