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Omega Engineering PCI-DAS1200 manual For Your Notes

Models: PCI-DAS1200

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— FOR YOUR NOTES —

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Omega Engineering PCI-DAS1200 manual For Your Notes

Contents

Users Guide PCI-DAS12004.2 WIRING CONFIGURATIONS 3.1 CONNECTOR PIN DIAGRAM6.1 CALIBRATION CONFIGURATION 3.0 HARDWARE CONNECTIONSTable of Contents ORFN3&,$LDJUDP6 1.0 INTRODUCTIONPCI BUS 5V, 32-BIT, 33MHZ 3&,%ORFN$LDJUDP6-5LOCAL BUS 2.1.2 Launching InstaCal 2.0 INSTALLATION2.1.1 Install the InstaCAL software 2.1.4 Testing the Installation 2.1.3 Using InstaCal2.2.3 Using InstaCal 2.2.1 Install the InstaCal software2.2.2 Launching InstaCal 2.2 DOS AND/OR WINDOWS2.2.4 TESTING THE INSTALLATION A nalog Input C h 0 Low / 8 H igh 3.0 HARDWARE CONNECTIONSA nalog Input C h 1 Low / 9 H igh A nalog Input C h 2 Low / 10 H igh4.1.1 Single-Ended and Differential Inputs 4.0 ANALOG CONNECTIONSSingle-Ended Inputs Single-Ended InputDifferential Input Differential InputsS in gle -ended input w ith C om m on M ode Voltage D iffe rential Inp utWhich system do you have? 4.1.2 System Grounds and IsolationSystems with Common Mode ground offset Voltages Systems with Common GroundsInput Configuration PCI-DAS1200 and signal source already have isolated groundsSmall Common Mode Voltages Large Common Mode Voltages4.2.2 Common Ground / Differential Inputs A /D BoardA /D Board A /D Board A /D Board4.2.3 Common Mode Voltage +/-10V / Single-Ended Inputs 4.2.4 Common Mode Voltage +/-10V / Differential InputsA /D Board A/D BoardA /D Board 4.2.6 Isolated Grounds / Single-Ended Inputs5.0 Programming & Applications 6.1 CALIBRATION CONFIGURATION 6.0 Self-Calibration of the PCI-DAS1200RefPGA Variable GainA n alo g O u t D A CR e f G ain A d j O ffset A dj7.2 BADR0 7.0 PCI-DAS1200 Register Description7.3 BADR1 7.3.1 INTERRUPT / ADC FIFO REGISTEREOAIE INTEEOACL INTCLADHFI EOBIADNEI ADNEResolution 7.3.3 TRIGGER CONTROL/STATUS REGISTERUNIBIP Input RangeTGEN TS10Source C0SRCXTRIG C0SRCINDXGT PRTRGDAC Channel 7.3.4 CALIBRATION REGISTERCal Function CSRC27.3.5 DAC CONTROL/STATUS REGISTER Does not apply to PCI-DAS1200/JR CALENDACEN MODE DACnR10 with SEL8800 and SEL7376 bits7.4.2 ADC FIFO CLEAR REGISTER 7.4 BADR27.4.1 ADC DATA REGISTER 7.5.1 ADC PACER CLOCK DATA AND CONTROL REGISTERS 7.5 BADR3Device Counter #DIO PORT A DATA ADC 8254 CONTROL REGISTER7.5.2 DIGITAL I/O DATA AND CONTROL REGISTERS DIO PORT C DATA DIO PORT B DATADIO CONTROL REGISTER BADR3 +8254B 7.5.3 INDEX and USER COUNTER DATA AND CONTROL REGISTERSCOUNTER 0 DATA-ADC8254B COUNTER 2 DATA - USER COUNTER #6 8254B COUNTER 1 DATA - USER COUNTER #58254B CONTROL REGISTER BADR3 +7.6.2 DAC1 DATA REGISTER 7.6 BADR47.6.1 DAC0 DATA REGISTER 8.0 Electrical Specifications Offset error Gain error Differential nonlinearity ANALOG OUTPUT Does not apply to PCI-DAS1200/JR ResolutionConfiguration Number of channels Output High Output Low Input High Input Low Power-up / reset state Interrupts Interrupt enableCounter type Configuration82C54 82C54APower consumption OTHER SPECIFICATIONSIcc Operating A/D converting to FIFO 0.8 A typical, 1.0 A maxFOR YOUR NOTES EC Declaration of Conformity