DIO Port B Data, DIO Port C Data | Omega Engineering PCI-DAS1200

DIO PORT B DATA

BADR3 + 5

PORT B may be configured as an 8-bit I/O channel. Its functionality is identical to that of PORT A.

READ/WRITE

7	6	5	4	2	3	1	0

D7	D6	D5	D4	D3	D2	D1	D0

DIO PORT C DATA

BADR3 + 6

PORT C may be configured as an 8-bit port of either input or output, or it may be split into two independent 4-bit ports of input or output. When split into two 4-bit I/O ports, D[3:0]

make up the lower nibble, D[7:4] comprise the upper nibble. Although it may be split, every write to Port C is a byte operation. Unwanted information must be ANDed out during reads and writes must be ORd with current value of the other 4-bit port.

READ/WRITE

7	6	5	4	2	3	1	0

D7	D6	D5	D4	D3	D2	D1	D0

DIO CONTROL REGISTER

BADR3 + 7

The DIO Control register is used configure Ports A,B and C as inputs or outputs. Operation is identical to that of the 8255 in Mode 0.

WRITE

7	6	5	4	2	3	1	0

D7	D6	D5	D4	D3	D2	D1	D0

The following table summarizes the possible I/O Port configurations for the PCI-DAS1200

DIO operatin in MODE 0:

30

Image 33

Omega Engineering PCI-DAS1200 manual DIO Port B Data, DIO Port C Data, DIO Control Register

Contents

Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Windows 95, 98 & NT Installation Using InstaCal DOS AND/OR Windows Testing the Installation Hardware Connections Connector PIN Diagram Analog Connections Differential Input Which system do you have? System Grounds and Isolation Systems with Common Grounds Systems with Common Mode ground offset Voltages Small Common Mode Voltages Wiring ConfigurationsLarge Common Mode Voltages PCI-DAS1200 and signal source already have isolated grounds Common Ground / Single-Ended Inputs Common Mode Voltage +/-10V Common Mode Voltage +/-10V / Single-Ended Inputs Board Programming Languages Programming & Applications Self-Calibration of the PCI-DAS1200 Alo g O u t BADR1 BADR0Interrupt / ADC Fifo Register Region Function Operations Eoaie InteEoacl Intcl ADC Channel MUX and Control Register EOC Input Range Input Gain Measurement ResolutionTrigger CONTROL/STATUS Register Pacer Source Tgen TS10 ARM Fifo Mode Sample CTRC0SRC Xtrig Calibration Register DAC Channel Cal FunctionCal Source Calen Dacen ModeSDI DACnR10 ADC Data Register BADR2BADR2 + ADC Fifo Clear Register ADC Pacer Clock Data and Control Registers BADR38254A Counter 0 Data ADC Post Trigger Conversion Counter BADR3 + Base + 8254A Counter 2 Data ADC Pacer Divider UpperADC 8254 Control Register Digital I/O Data and Control Registers DIO Port B Data DIO Port C DataDIO Control Register Counter DATA-ADC Index and User Counter Data and Control Registers 8254BPRE-TRIGGER Index Counter Or User 8254B Counter 2 Data User Counter #6 8254B Counter 1 Data User Counter #5BADR3 + Ah 8254B Control Register BADR4 1 DAC0 Data Register2 DAC1 Data Register Analog Input Section Electrical Specifications Parallel Digital Input / Output Analog Output 82C54A Counter Section Other Specifications Power consumptionEnvironmental For Your Notes EC Declaration of Conformity