Alo g O u t | Omega Engineering PCI-DAS1200 instruction

The calibration scheme for the Analog Out (not applicable on the PCI-DAS1200/JR) section is shown in Figure 2 below. This circuit is duplicated for both DAC0 and DAC1

T rim D a c (c o a rse )

T rim D a c

(fin e )

1 2

D A C				A n alo g O u t
D A C				A n alo g O u t
R e f

G ain A d j.

O ffset A dj.

T rim D a c

Figure 2

Page 21

Image 21

Omega Engineering PCI-DAS1200 manual Alo g O u t

Contents

Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Windows 95, 98 & NT Installation Using InstaCal DOS AND/OR Windows Testing the Installation Hardware Connections Connector PIN Diagram Analog Connections Differential Input Which system do you have? System Grounds and Isolation Systems with Common Grounds Systems with Common Mode ground offset Voltages Small Common Mode Voltages Wiring ConfigurationsLarge Common Mode Voltages PCI-DAS1200 and signal source already have isolated grounds Common Ground / Single-Ended Inputs Common Mode Voltage +/-10V Common Mode Voltage +/-10V / Single-Ended Inputs Board Programming Languages Programming & Applications Self-Calibration of the PCI-DAS1200 Alo g O u t BADR1 BADR0Interrupt / ADC Fifo Register Region Function Operations Eoaie InteEoacl Intcl ADC Channel MUX and Control Register EOC Input Range Input Gain Measurement ResolutionTrigger CONTROL/STATUS Register Pacer Source Tgen TS10 ARM Fifo Mode Sample CTRC0SRC Xtrig Calibration Register DAC Channel Cal FunctionCal Source Calen Dacen ModeSDI DACnR10 ADC Data Register BADR2BADR2 + ADC Fifo Clear Register ADC Pacer Clock Data and Control Registers BADR38254A Counter 0 Data ADC Post Trigger Conversion Counter BADR3 + Base + 8254A Counter 2 Data ADC Pacer Divider UpperADC 8254 Control Register Digital I/O Data and Control Registers DIO Port B Data DIO Port C DataDIO Control Register Counter DATA-ADC Index and User Counter Data and Control Registers 8254BPRE-TRIGGER Index Counter Or User 8254B Counter 2 Data User Counter #6 8254B Counter 1 Data User Counter #5BADR3 + Ah 8254B Control Register BADR4 1 DAC0 Data Register2 DAC1 Data Register Analog Input Section Electrical Specifications Parallel Digital Input / Output Analog Output 82C54A Counter Section Other Specifications Power consumptionEnvironmental For Your Notes EC Declaration of Conformity

A n alo g O u t