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Omega Engineering PCI-DAS1200 manual

Models: PCI-DAS1200

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Contents

Users Guide PCI-DAS12003.0 HARDWARE CONNECTIONS 3.1 CONNECTOR PIN DIAGRAM4.2 WIRING CONFIGURATIONS 6.1 CALIBRATION CONFIGURATIONTable of Contents ORFN3&,$LDJUDP6 1.0 INTRODUCTIONLOCAL BUS 3&,%ORFN$LDJUDP6-5PCI BUS 5V, 32-BIT, 33MHZ 2.1.1 Install the InstaCAL software 2.0 INSTALLATION2.1.2 Launching InstaCal 2.1.4 Testing the Installation 2.1.3 Using InstaCal2.2 DOS AND/OR WINDOWS 2.2.1 Install the InstaCal software2.2.3 Using InstaCal 2.2.2 Launching InstaCal2.2.4 TESTING THE INSTALLATION A nalog Input C h 2 Low / 10 H igh 3.0 HARDWARE CONNECTIONSA nalog Input C h 0 Low / 8 H igh A nalog Input C h 1 Low / 9 H ighSingle-Ended Input 4.0 ANALOG CONNECTIONS4.1.1 Single-Ended and Differential Inputs Single-Ended InputsD iffe rential Inp ut Differential InputsDifferential Input S in gle -ended input w ith C om m on M ode VoltageWhich system do you have? 4.1.2 System Grounds and IsolationSystems with Common Mode ground offset Voltages Systems with Common GroundsLarge Common Mode Voltages PCI-DAS1200 and signal source already have isolated groundsInput Configuration Small Common Mode VoltagesA /D Board A /D Board4.2.2 Common Ground / Differential Inputs 4.2.4 Common Mode Voltage +/-10V / Differential Inputs A /D BoardA /D Board 4.2.3 Common Mode Voltage +/-10V / Single-Ended Inputs4.2.6 Isolated Grounds / Single-Ended Inputs A/D BoardA /D Board A /D Board5.0 Programming & Applications Variable Gain 6.0 Self-Calibration of the PCI-DAS12006.1 CALIBRATION CONFIGURATION RefPGAG ain A d j O ffset A dj D A CA n alo g O u t R e f7.3.1 INTERRUPT / ADC FIFO REGISTER 7.0 PCI-DAS1200 Register Description7.2 BADR0 7.3 BADR1INTCL INTEEOAIE EOACLADNE EOBIADHFI ADNEIInput Range 7.3.3 TRIGGER CONTROL/STATUS REGISTERResolution UNIBIPC0SRC TS10TGEN SourcePRTRG C0SRCXTRIG INDXGTCSRC2 7.3.4 CALIBRATION REGISTERDAC Channel Cal Functionwith SEL8800 and SEL7376 bits CALEN7.3.5 DAC CONTROL/STATUS REGISTER Does not apply to PCI-DAS1200/JR DACEN MODE DACnR107.4.1 ADC DATA REGISTER 7.4 BADR27.4.2 ADC FIFO CLEAR REGISTER Counter # 7.5 BADR37.5.1 ADC PACER CLOCK DATA AND CONTROL REGISTERS Device7.5.2 DIGITAL I/O DATA AND CONTROL REGISTERS ADC 8254 CONTROL REGISTERDIO PORT A DATA BADR3 + DIO PORT B DATADIO PORT C DATA DIO CONTROL REGISTER0 DATA-ADC 7.5.3 INDEX and USER COUNTER DATA AND CONTROL REGISTERS8254B COUNTERBADR3 + 8254B COUNTER 1 DATA - USER COUNTER #58254B COUNTER 2 DATA - USER COUNTER #6 8254B CONTROL REGISTER7.6.1 DAC0 DATA REGISTER 7.6 BADR47.6.2 DAC1 DATA REGISTER 8.0 Electrical Specifications Input Low Power-up / reset state Interrupts Interrupt enable ANALOG OUTPUT Does not apply to PCI-DAS1200/JR ResolutionOffset error Gain error Differential nonlinearity Configuration Number of channels Output High Output Low Input High82C54A ConfigurationCounter type 82C54Storage temperature range OTHER SPECIFICATIONSPower consumption Operating temperature rangeFOR YOUR NOTES EC Declaration of Conformity