Table of Contents | Omega Engineering PCI-DAS1200 specs

Table of Contents
7.3.4 CALIBRATION REGISTER	. . . . . . . . . . . 25
7.3.5 DAC CONTROL/STATUS REGISTER (Does not apply	to
PCI-DAS1200/JR)	. . . . . . . . . . . 26
7.4 BADR2	. . . . . . . . . . . 27
7.4.1 ADC DATA REGISTER	. . . . . . . . . . . 27
7.4.2 ADC FIFO CLEAR REGISTER	. . . . . . . . . . . 27
7.5 BADR3	. . . . . . . . . . . 28
7.5.1 ADC PACER CLOCK DATA AND CONTROL REGISTERS . .	. . . . . . . . . . . 28
7.5.2 DIGITAL I/O DATA AND CONTROL REGISTERS	. . . . . . . . . . . 29
7.6 BADR4	. . . . . . . . . . . 33
7.6.1 DAC0 DATA REGISTER	. . . . . . . . . . . 33
7.6.2 DAC1 DATA REGISTER	. . . . . . . . . . . 33
8.0 ELECTRICAL SPECIFICATIONS	. . . . . . . . . . . 34
ANALOG INPUT SECTION	. . . . . . . . . . . 34
ANALOG OUTPUT:	. . . . . . . . . . . 35
PARALLEL DIGITAL INPUT / OUTPUT	. . . . . . . . . . . 35
COUNTER SECTION	. . . . . . . . . . . 36
OTHER SPECIFICATIONS:	. . . . . . . . . . . 37

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Omega Engineering PCI-DAS1200 manual Table of Contents

Contents

Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Windows 95, 98 & NT Installation Using InstaCal DOS AND/OR Windows Testing the Installation Hardware Connections Connector PIN Diagram Analog Connections Differential Input Which system do you have? System Grounds and Isolation Systems with Common Grounds Systems with Common Mode ground offset Voltages PCI-DAS1200 and signal source already have isolated grounds Wiring ConfigurationsSmall Common Mode Voltages Large Common Mode Voltages Common Ground / Single-Ended Inputs Common Mode Voltage +/-10V Common Mode Voltage +/-10V / Single-Ended Inputs Board Programming Languages Programming & Applications Self-Calibration of the PCI-DAS1200 Alo g O u t Region Function Operations BADR0BADR1 Interrupt / ADC Fifo Register Intcl InteEoaie Eoacl ADC Channel MUX and Control Register Pacer Source Input Range Input Gain Measurement ResolutionEOC Trigger CONTROL/STATUS Register Tgen TS10 Xtrig Fifo Mode Sample CTRARM C0SRC Calibration Register DAC Channel Cal FunctionCal Source DACnR10 Dacen ModeCalen SDI ADC Fifo Clear Register BADR2ADC Data Register BADR2 + BADR3 + BADR3ADC Pacer Clock Data and Control Registers 8254A Counter 0 Data ADC Post Trigger Conversion Counter Digital I/O Data and Control Registers 8254A Counter 2 Data ADC Pacer Divider UpperBase + ADC 8254 Control Register DIO Port B Data DIO Port C DataDIO Control Register Or User Index and User Counter Data and Control Registers 8254BCounter DATA-ADC PRE-TRIGGER Index Counter 8254B Control Register 8254B Counter 1 Data User Counter #58254B Counter 2 Data User Counter #6 BADR3 + Ah BADR4 1 DAC0 Data Register2 DAC1 Data Register Analog Input Section Electrical Specifications Parallel Digital Input / Output Analog Output 82C54A Counter Section Other Specifications Power consumptionEnvironmental For Your Notes EC Declaration of Conformity