Intel manual Intel 41210 Serial to Parallel PCI Bridge, Design Guide

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Intel® 41210 Serial to Parallel PCI Bridge

Design Guide

May 2005

Order Number: 278801-004

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Contents Design Guide Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents Figures Revision History TablesDescription This page intentionally left blank Terminology and Definitions About This DocumentTerminology and Definitions Sheet 1 Term DefinitionTerminology and Definitions Sheet 2 About This DocumentPCI-X Interface Features PCI Express Interface FeaturesIntroduction2 SMBus for configuration register initialization Power ManagementSMBus Interface IntroductionMicrocontroller Connections to the 41210 Bridge Bridge Microcontroller Block DiagramRelated Documents JtagIntel41210 Serial to Parallel PCI Bridge Applications Intel 41210 Bridge Adapter Card Block DiagramThis page intentionally left blank Package Information Package SpecificationPackage Information Bottom View 41210 Bridge 567-Ball Fcbga Package DimensionsSide View 41210 Bridge 567-Ball Fcbga Package Dimensions This page intentionally left blank 41210 Bridge Decoupling Guidelines Power Plane LayoutPower Plane Layout Bridge Decoupling Guidelines Split Voltage PlanesPCI ARST#,BRST# and PERST# Timing Requirements Bridge Reset and Power Timing Considerations5VCC15 and VCC33 Voltage Requirements Bridge Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI ConsiderationsTrace Impedance Power Distribution and DecouplingDecoupling Cross Section of Differential Trace Differential ImpedanceAdapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout GuidelinesInterrupts PCI-X Layout GuidelinesINTx Routing Table Interrupt Routing for Devices Behind a Bridge PCI ArbitrationPCI-X Layout Guidelines Interrupt Binding for Devices Behind a BridgePCI Resistor Compensation PCI General Layout GuidelinesPCI Pullup Resistors Not Required PCI-X SignalsPCI/PCI-X Frequency/Mode Straps BCBE#74, BDEVSEL#, BFRAME#, BINTA#, BINTB#, BINTC#, BINTD# PCI Clock Layout GuidelinesPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements SummaryPCI-X Slot Guidelines PCI-X Topology Layout GuidelinesEmbedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 133 MHzParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyThis page intentionally left blank General recommendations PCI Express LayoutAdapter Card Layout Guidelines PCI-Express Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations Config10.1 41210 Bridge Analog Voltage Filters PCI Express Analog Voltage Filter PCI Analog Voltage FiltersCircuit Implementations Vccape Bandgap Analog Voltage FilterVssape Vccbgpe Bandgap Analog Voltage Filter CircuitVSS Vssbgpe PERCOMP0 PERCOMP1 Rcomp Reference and Compensation Circuit ImplementationsSM Bus SMBUs Address ConfigurationBit Value Board Stack-up Bridge Customer Reference BoardsMaterial Layer Type Thickness Copper WeightImpedance Bridge Customer Reference BoardsMechanical Outline of the 41210 Bridge Board OutlineThis page intentionally left blank PCI Express Interface Signals Design Guide ChecklistSignals Recommendations Reason/Impact PERCOMP10PCI/PCI-X Interface Signals Design Guide ChecklistBM66EN PERST# AM66ENApcixcap BpcixcapSMBus Interface Signals Miscellaneous SignalsSignals Signal Recommendations Reason/Impact Power and Ground SignalsVCC15 VCC33Jtag Signals
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