Intel 41210 manual Embedded PCI-X 133 MHz Routing Recommendations

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PCI-X Layout Guidelines

8.6.1Embedded PCI-X 133 MHz

This section lists the routing recommendations for PCI-X 133 MHz without a slot. Figure 18 shows the block diagram of this topology and Table 10 describes the routing recommendations.

Figure 18. Embedded PCI-X 133 MHz Topology

		EM1
		TL EM1
		TL1
		TL EM2
		EM2
			B2719 -01

Table 10.	Embedded PCI-X 133 MHz Routing Recommendations

	Parameter	Routing Guideline for Lower AD Bus

	Reference Plane	Route over an unbroken ground plane

	Board Impedance	60 Ω +/- 15%

	Stripline Trace Spacing	12 mils from edge to edge

	Microstrip Trace Spacing	18 mils, from edge to edge

	Break Out	5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils

	Group Spacing	Spacing from other groups: 25 mils min, edge to edge

	Trace Length 1 (TL1): From
	41210 Bridge signal Ball to	1.75” min - 4.0” max
	first junction

	Trace Length 3 junction of
	TL_EM1 and TL_EM2 to the	1.25” min - 3.25” max
	embedded device
	Length Matching	Clocks coming form the clock driver must be on the same layer and length
	Requirements:	matched to within 25 mils.

	Number of vias	3 vias max per path

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Contents Design Guide Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents Figures Tables Revision HistoryDescription This page intentionally left blank Term Definition About This DocumentTerminology and Definitions Terminology and Definitions Sheet 1Terminology and Definitions Sheet 2 About This DocumentPCI Express Interface Features PCI-X Interface FeaturesIntroduction2 Introduction Power ManagementSMBus for configuration register initialization SMBus InterfaceMicrocontroller Connections to the 41210 Bridge Bridge Microcontroller Block DiagramRelated Documents JtagIntel41210 Serial to Parallel PCI Bridge Applications Intel 41210 Bridge Adapter Card Block DiagramThis page intentionally left blank Package Information Package SpecificationPackage Information Bottom View 41210 Bridge 567-Ball Fcbga Package DimensionsSide View 41210 Bridge 567-Ball Fcbga Package Dimensions This page intentionally left blank 41210 Bridge Decoupling Guidelines Power Plane LayoutPower Plane Layout Bridge Decoupling Guidelines Split Voltage PlanesPCI Bridge Reset and Power Timing Considerations5 ARST#,BRST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Bridge Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI ConsiderationsPower Distribution and Decoupling Trace ImpedanceDecoupling Cross Section of Differential Trace Differential ImpedanceBoard Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout GuidelinesPCI-X Layout Guidelines InterruptsINTx Routing Table Interrupt Binding for Devices Behind a Bridge PCI ArbitrationInterrupt Routing for Devices Behind a Bridge PCI-X Layout GuidelinesPCI Resistor Compensation PCI General Layout GuidelinesPCI-X Signals PCI Pullup Resistors Not RequiredPCI/PCI-X Frequency/Mode Straps BCBE#74, BDEVSEL#, BFRAME#, BINTA#, BINTB#, BINTC#, BINTD# PCI Clock Layout GuidelinesPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements SummaryPCI-X Slot Guidelines PCI-X Topology Layout GuidelinesEmbedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyThis page intentionally left blank General recommendations PCI Express LayoutAdapter Card Routing Recommendations Sheet 1 PCI-Express Layout GuidelinesAdapter Card Layout Guidelines PCI Express LayoutAdapter Card Routing Recommendations Sheet 2 This page intentionally left blank Config Circuit Implementations10.1 41210 Bridge Analog Voltage Filters PCI Analog Voltage Filters PCI Express Analog Voltage FilterCircuit Implementations Bandgap Analog Voltage Filter VccapeVssape Bandgap Analog Voltage Filter Circuit VccbgpeVSS Vssbgpe PERCOMP0 PERCOMP1 Rcomp Reference and Compensation Circuit ImplementationsSMBUs Address Configuration SM BusBit Value Board Stack-up Bridge Customer Reference BoardsBridge Customer Reference Boards Layer Type Thickness Copper WeightMaterial ImpedanceMechanical Outline of the 41210 Bridge Board OutlineThis page intentionally left blank PERCOMP10 Design Guide ChecklistPCI Express Interface Signals Signals Recommendations Reason/ImpactPCI/PCI-X Interface Signals Design Guide ChecklistBpcixcap AM66ENBM66EN PERST# ApcixcapMiscellaneous Signals SMBus Interface SignalsSignals VCC33 Power and Ground SignalsSignal Recommendations Reason/Impact VCC15Jtag Signals

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