About This Document
Table 1. Terminology and Definitions (Sheet 2 of 2)
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| Definition | |||||
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| Layer 1: copper | Printed circuit board. | ||||||
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| Example manufacturing process consists of | |||||||
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| Prepreg | the following steps: | ||||||
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| Layer 2: GND | |||||||
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| • Consists of alternating layers of core and | ||||||
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| Core |
| prepreg stacked | |||||
PCB |
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| Layer 3: VCC15 |
| • The finished PCB is heated and cured. | |||||
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| • The via holes are drilled | |||||||
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| Prepreg |
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| Layer 4: copper |
| • Plating covers holes and outer surfaces | |||||
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| • Etching removes unwanted copper | |||
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| Example of a |
| • Board is tinned, coated with solder mask | ||||||||
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| and silk screened | |||||||||
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SSTL_2 | Series Stub Terminated Logic for 2.5 V |
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JEDEC | Provides standards for the semiconductor industry. | ||||||||||||
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| A network that transmits a coupled signal to another network is aggressor network. | ||||||||||||
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| Zo |
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Aggressor |
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| Zo |
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| Zo |
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| Zo | ||||
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| Victim Network |
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| Aggressor Network |
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Victim | A network that receives a coupled | ||||||||||||
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Network | The trace of a PCB that completes an electrical connection between two or more components. | ||||||||||||
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Stub | Branch from a trunk terminating at the pad of an agent. | ||||||||||||
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CRB | Customer Reference Board |
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| Downstream refers either to the relative position of an interconnect/system element (Link/ | ||||||||||||
Downstream | device) as something that is farther from the Root Complex, or to a direction of information | ||||||||||||
| flow, i.e., when information is flowing away from the Root Complex. | ||||||||||||
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Upstream |
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Local memory | Memory subsystem on the Intel XScale® core DDR SDRAM or Peripheral Bus Interface | ||||||||||||
busses. |
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DWORD |
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Flip Chip | on the back of the chip, facing away from the PCB. This allows more efficient cooling of the | ||||||||||||
| package. |
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Mode | Mode Conversions are due to imperfections on the interconnect which transform differential | ||||||||||||
Conversion | mode voltage to common mode voltage and common mode voltage to differential voltage. | ||||||||||||
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8 | Intel® 41210 Serial to Parallel PCI Bridge Design Guide |