Intel 41210 manual Introduction2, PCI Express Interface Features, PCI-X Interface Features

Introduction2

The Intel®41210 Serial to Parallel PCI Bridge integrates two PCI Express-to-PCI bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compliant to the PCI Express Specification, Revision 1.0. The two PCI bus interfaces are fully compliant to the PCI Local Bus Specification, Revision 2.3.

2.1PCI Express Interface Features

•PCI Express Specification, Revision 1.0b compliant.

•Support for single x8, single x4 or single x1 PCI Express operation.

•64-bit addressing support.

•32-bit CRC (cyclic redundancy checking) covering all transmitted data packets.

•16-bit CRC on all link message information.

•Raw bit-rate on the data pins of 2.5 Gbit/s, resulting in a raw bandwidth per pin of 250 MB/s.

•Maximum realized bandwidth on PCI Express interface is 2 GB/s (in x8 mode) in each direction simultaneously, for an aggregate of 4 GB/s.

2.2PCI-X Interface Features

•PCI Local Bus Specification, Revision 2.3 compliant.

•PCI-to-PCI Bridge Specification, Revision 1.1 compliant.

•PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a compliant.

•64-bit 66 MHz, 3.3 V, NOT 5 V tolerant.

•On Die Termination (ODT) with 8.2KΩ pull-up to 3.3V for PCI signals.

•Six external REQ/GNT Pairs for internal arbiter on segment A and B respectively.

•Programmable bus parking on either the last agent or always on Lanai.

•2-level programmable round-robin internal arbiter with Multi-Transaction Timer (MTT)

•External PCI clock-feed support for asynchronous primary and secondary domain operation.

•64-bit addressing for upstream and downstream transactions

•Downstream LOCK# support.

•No upstream LOCK# support.

•PCI fast Back-to-Back capable as target.

•Up to four active and four pending upstream memory read transactions

•Up to two downstream delayed (memory read, I/O read/write and configuration read/write) transaction.

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 9