Intel 41210 manual Adapter Card Routing Recommendations Sheet 2

Page 47

PCI Express Layout

Table 15. Adapter Card Routing Recommendations (Sheet 2 of 2)

Receive Trace Length (Card
edge finger to 41210 Bridge	1.0” min - 6.0” max
receiver pin
Length Matching	Total allowable intra-pair length mis-match must not exceed 25 mils. Each
Length Matching	routing segment should be matched as close as possible. Total skew across all
Requirements:	lanes must be less than 20 ns. See the PCI-Express Desktop Design Guidelines
	for additional routing requirements

Number of vias	4 max

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Image 47

Contents Design Guide Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents Figures Description TablesRevision History This page intentionally left blank Term Definition About This DocumentTerminology and Definitions Terminology and Definitions Sheet 1Terminology and Definitions Sheet 2 About This DocumentIntroduction2 PCI Express Interface FeaturesPCI-X Interface Features Introduction Power ManagementSMBus for configuration register initialization SMBus InterfaceMicrocontroller Connections to the 41210 Bridge Bridge Microcontroller Block DiagramRelated Documents JtagIntel41210 Serial to Parallel PCI Bridge Applications Intel 41210 Bridge Adapter Card Block DiagramThis page intentionally left blank Package Information Package SpecificationPackage Information Bottom View 41210 Bridge 567-Ball Fcbga Package DimensionsSide View 41210 Bridge 567-Ball Fcbga Package Dimensions This page intentionally left blank 41210 Bridge Decoupling Guidelines Power Plane LayoutPower Plane Layout Bridge Decoupling Guidelines Split Voltage PlanesPCI VCC15 and VCC33 Voltage Requirements Bridge Reset and Power Timing Considerations5ARST#,BRST# and PERST# Timing Requirements Bridge Reset and Power Timing Considerations Crosstalk General Routing GuidelinesGeneral Routing Guidelines General Routing Guidelines EMI ConsiderationsDecoupling Power Distribution and DecouplingTrace Impedance Cross Section of Differential Trace Differential ImpedanceAdapter Card Stack Up, Microstrip and Stripline Board Layout GuidelinesAdapter Card Topology Adapter Card Stackup Board Layout GuidelinesINTx Routing Table PCI-X Layout GuidelinesInterrupts Interrupt Binding for Devices Behind a Bridge PCI ArbitrationInterrupt Routing for Devices Behind a Bridge PCI-X Layout GuidelinesPCI Resistor Compensation PCI General Layout GuidelinesPCI/PCI-X Frequency/Mode Straps PCI-X SignalsPCI Pullup Resistors Not Required BCBE#74, BDEVSEL#, BFRAME#, BINTA#, BINTB#, BINTC#, BINTD# PCI Clock Layout GuidelinesPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements SummaryPCI-X Slot Guidelines PCI-X Topology Layout GuidelinesParameter Routing Guideline for Lower AD Bus Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyThis page intentionally left blank General recommendations PCI Express LayoutAdapter Card Routing Recommendations Sheet 1 PCI-Express Layout GuidelinesAdapter Card Layout Guidelines PCI Express LayoutAdapter Card Routing Recommendations Sheet 2 This page intentionally left blank 10.1 41210 Bridge Analog Voltage Filters ConfigCircuit Implementations Circuit Implementations PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Vssape Bandgap Analog Voltage FilterVccape VSS Vssbgpe Bandgap Analog Voltage Filter CircuitVccbgpe PERCOMP0 PERCOMP1 Rcomp Reference and Compensation Circuit ImplementationsBit Value SMBUs Address ConfigurationSM Bus Board Stack-up Bridge Customer Reference BoardsBridge Customer Reference Boards Layer Type Thickness Copper WeightMaterial ImpedanceMechanical Outline of the 41210 Bridge Board OutlineThis page intentionally left blank PERCOMP10 Design Guide ChecklistPCI Express Interface Signals Signals Recommendations Reason/ImpactPCI/PCI-X Interface Signals Design Guide ChecklistBpcixcap AM66ENBM66EN PERST# ApcixcapSignals Miscellaneous SignalsSMBus Interface Signals VCC33 Power and Ground SignalsSignal Recommendations Reason/Impact VCC15Jtag Signals

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