Intel 41210 manual PCI 33 MHz Embedded Mode Topology, PCI 33 MHz Embedded Routing Recommendations

PCI-X Layout Guidelines

8.6.5PCI 33 MHz Embedded Mode Topology

Figure 22 and Table 14 provide routing details for a topology with an embedded PCI 33 MHz design.

Figure 22. PCI 33 MHz Embedded Mode Routing Topology

	EM1	EM3	EM5	EM7	EM9
	TL EM1	TL EM3	TL EM5	TL EM7	TL EM9
TL1	TL2	TL3	TL4		TL5
	TL EM2	TL EM4	TL EM6	TL EM8	TL EM10
	EM2	EM4	EM6	EM8	EM10
					B2723 -01

Table 14.	PCI 33 MHz Embedded Routing Recommendations
	Parameter	Routing Guideline for Lower AD Bus
	Reference Plane	Route over an unbroken ground plane
	Board Impedance	60 Ω +/- 15%
	Stripline Trace Spacing	12 mils, edge to edge
	Microstrip Trace Spacing	18 mils edge to edge
	Group Spacing	Spacing from other groups: 25 mils min, edge to edge
	Breakout	5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils.
	Trace Length 1 TL1: From
	41210 Bridge signal Ball to	5.0” max
	first junction
	Trace Length TL2 to TL5 -	0.5” min - 3.5” max
	between junctions
	Trace Length TL_EM1 to
	TL_EM10 from junction to	2.0” min - 3.0” max
	embedded devices
	Length Matching	Clocks coming from the clock driver must be length matched to within 25 mils.
	Requirements

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 43