Intel 41210 manual Power Plane Layout

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Power Plane Layout

Figure 9. Decoupling Placement for PCI/PCI-X 1.5V and 3.3V Voltage Planes

Capacitor Legend

0603-0.1 F

0603-1 F

1206-10 F

B2714-01

20	Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Contents Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents Figures Description TablesRevision History This page intentionally left blank About This Document Terminology and DefinitionsTerminology and Definitions Sheet 1 Term DefinitionAbout This Document Terminology and Definitions Sheet 2Introduction2 PCI Express Interface FeaturesPCI-X Interface Features Power Management SMBus for configuration register initializationSMBus Interface IntroductionBridge Microcontroller Block Diagram Microcontroller Connections to the 41210 BridgeJtag Related DocumentsIntel 41210 Bridge Adapter Card Block Diagram Intel41210 Serial to Parallel PCI Bridge ApplicationsThis page intentionally left blank Package Specification Package InformationBottom View 41210 Bridge 567-Ball Fcbga Package Dimensions Package InformationSide View 41210 Bridge 567-Ball Fcbga Package Dimensions This page intentionally left blank Power Plane Layout 41210 Bridge Decoupling GuidelinesPower Plane Layout Split Voltage Planes Bridge Decoupling GuidelinesPCI VCC15 and VCC33 Voltage Requirements Bridge Reset and Power Timing Considerations5ARST#,BRST# and PERST# Timing Requirements Bridge Reset and Power Timing Considerations Crosstalk General Routing GuidelinesGeneral Routing Guidelines EMI Considerations General Routing GuidelinesDecoupling Power Distribution and DecouplingTrace Impedance Differential Impedance Cross Section of Differential TraceAdapter Card Stack Up, Microstrip and Stripline Board Layout GuidelinesAdapter Card Topology Board Layout Guidelines Adapter Card StackupINTx Routing Table PCI-X Layout GuidelinesInterrupts PCI Arbitration Interrupt Routing for Devices Behind a BridgePCI-X Layout Guidelines Interrupt Binding for Devices Behind a BridgePCI General Layout Guidelines PCI Resistor CompensationPCI/PCI-X Frequency/Mode Straps PCI-X SignalsPCI Pullup Resistors Not Required PCI Clock Layout Guidelines BCBE#74, BDEVSEL#, BFRAME#, BINTA#, BINTB#, BINTC#, BINTD#PCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing GuidelinesPCI-X Topology Layout Guidelines PCI-X Slot GuidelinesParameter Routing Guideline for Lower AD Bus Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing RecommendationsPCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing RecommendationsPCI 66 MHz Embedded Topology PCI 66 MHz Embedded TablePCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing RecommendationsThis page intentionally left blank PCI Express Layout General recommendationsPCI-Express Layout Guidelines Adapter Card Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank 10.1 41210 Bridge Analog Voltage Filters ConfigCircuit Implementations Circuit Implementations PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Vssape Bandgap Analog Voltage FilterVccape VSS Vssbgpe Bandgap Analog Voltage Filter CircuitVccbgpe Reference and Compensation Circuit Implementations PERCOMP0 PERCOMP1 RcompBit Value SMBUs Address ConfigurationSM Bus Bridge Customer Reference Boards Board Stack-upLayer Type Thickness Copper Weight MaterialImpedance Bridge Customer Reference BoardsBoard Outline Mechanical Outline of the 41210 BridgeThis page intentionally left blank Design Guide Checklist PCI Express Interface SignalsSignals Recommendations Reason/Impact PERCOMP10Design Guide Checklist PCI/PCI-X Interface SignalsAM66EN BM66EN PERST#Apcixcap BpcixcapSignals Miscellaneous SignalsSMBus Interface Signals Power and Ground Signals Signal Recommendations Reason/ImpactVCC15 VCC33Jtag Signals

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