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18	Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Contents Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents Figures Tables Revision HistoryDescription This page intentionally left blank Terminology and Definitions Sheet 1 About This DocumentTerminology and Definitions Term DefinitionAbout This Document Terminology and Definitions Sheet 2PCI Express Interface Features PCI-X Interface FeaturesIntroduction2 SMBus Interface Power ManagementSMBus for configuration register initialization IntroductionBridge Microcontroller Block Diagram Microcontroller Connections to the 41210 BridgeJtag Related DocumentsIntel 41210 Bridge Adapter Card Block Diagram Intel41210 Serial to Parallel PCI Bridge ApplicationsThis page intentionally left blank Package Specification Package InformationBottom View 41210 Bridge 567-Ball Fcbga Package Dimensions Package InformationSide View 41210 Bridge 567-Ball Fcbga Package Dimensions This page intentionally left blank Power Plane Layout 41210 Bridge Decoupling GuidelinesPower Plane Layout Split Voltage Planes Bridge Decoupling GuidelinesPCI Bridge Reset and Power Timing Considerations5 ARST#,BRST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Bridge Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk EMI Considerations General Routing GuidelinesPower Distribution and Decoupling Trace ImpedanceDecoupling Differential Impedance Cross Section of Differential TraceBoard Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Adapter Card StackupPCI-X Layout Guidelines InterruptsINTx Routing Table PCI-X Layout Guidelines PCI ArbitrationInterrupt Routing for Devices Behind a Bridge Interrupt Binding for Devices Behind a BridgePCI General Layout Guidelines PCI Resistor CompensationPCI-X Signals PCI Pullup Resistors Not RequiredPCI/PCI-X Frequency/Mode Straps PCI Clock Layout Guidelines BCBE#74, BDEVSEL#, BFRAME#, BINTA#, BINTB#, BINTC#, BINTD#PCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing GuidelinesPCI-X Topology Layout Guidelines PCI-X Slot GuidelinesEmbedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing RecommendationsPCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing RecommendationsPCI 66 MHz Embedded Topology PCI 66 MHz Embedded TablePCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing RecommendationsThis page intentionally left blank PCI Express Layout General recommendationsPCI Express Layout PCI-Express Layout GuidelinesAdapter Card Layout Guidelines Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Config Circuit Implementations10.1 41210 Bridge Analog Voltage Filters PCI Analog Voltage Filters PCI Express Analog Voltage FilterCircuit Implementations Bandgap Analog Voltage Filter VccapeVssape Bandgap Analog Voltage Filter Circuit VccbgpeVSS Vssbgpe Reference and Compensation Circuit Implementations PERCOMP0 PERCOMP1 RcompSMBUs Address Configuration SM BusBit Value Bridge Customer Reference Boards Board Stack-upImpedance Layer Type Thickness Copper WeightMaterial Bridge Customer Reference BoardsBoard Outline Mechanical Outline of the 41210 BridgeThis page intentionally left blank Signals Recommendations Reason/Impact Design Guide ChecklistPCI Express Interface Signals PERCOMP10Design Guide Checklist PCI/PCI-X Interface SignalsApcixcap AM66ENBM66EN PERST# BpcixcapMiscellaneous Signals SMBus Interface SignalsSignals VCC15 Power and Ground SignalsSignal Recommendations Reason/Impact VCC33Jtag Signals

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