PCI-X Layout Guidelines
Figure 17. PCI Clock Distribution and Matching Requirements
A_CLKIN
Intel® 41210 Bridge
A_CLKO0
A_CLKO1
A_CLKO2 d A_CLKO3 A_CLKO4
A_CLKO6
22
22 |
| X0 |
22 |
| a |
| ||
| X1 |
22
| X2 |
22 | X3 |
22 | X4 |
PCI
Device 1
PCI
Device 2
PCI
Device 3
PCI
Device 4
PCI
Device 5
PCI Bus
Notes:
–PCI Clock Lengths X0, X1, X2, X3 and X4 should be matched within 0.1 inch of each other.
–Minimum separation between two different CLKs, "d".
–Minimum separation between two segments of the same CLK line, "a".
36 | Intel® 41210 Serial to Parallel PCI Bridge Design Guide |