Intel 41210 Power and Ground Signals, Signal Recommendations Reason/Impact, VCC15, VCC33, Vccpe

Page 63

 

 

 

Design Guide Checklist

Table 23. Power and Ground Signals

 

 

 

 

 

 

Signal

Recommendations

Reason/Impact

 

 

 

 

 

 

100±1% (1/4 W) pulldown resistor to ground.

Analog compensation pin for

 

RCOMP

 

 

 

PCI. 0.75V nominal.

 

 

The trace impedance of this signal should be < 0.1Ω.

 

 

 

 

 

 

 

 

 

Connect to 1.5V power supply.

 

 

 

Note: Linear voltage regulators are recommended

 

 

 

when using 1.5 Volt power supplies.

 

 

 

Decoupling:

 

 

VCC15

5 0.1uF caps beneath package (backside of board)

1.5V ±5% core voltage.

 

 

2 1.0 uF caps as close as design rules permit to

 

 

 

package

 

 

 

3 10 uF caps as close as design rules permit to

 

 

 

package

 

 

 

 

 

 

 

Connect to 3.3V power supply.

 

 

 

Decoupling: TBD

 

 

 

The platform must insure that the VCC33 voltage rail

 

 

 

be greater than to (or no less than 0.5V below) VCC15

 

 

VCC33

(absolute voltage value at all times during 41210

3.3V ±5% PCI I/O voltage.

 

Bridge operation, including during system power up,

 

 

power down or any other time during system operation.

 

 

 

This can be accomplished by placing a diode (with a

 

 

 

voltage drop < 0.5V) between VCC15 and VCC33.

 

 

 

Anode will be connected to VCC15 and cathode will be

 

 

 

connected to VCC33.

 

 

 

 

 

 

VCCAPE

Connect to 1.5V power supply.

1.5V ±3% Analog PCI Express

 

 

voltage.

 

 

 

 

 

 

 

 

VCCAPCI[2:0]

See Figure 23 for circuit.

Analog PCI voltage pins.

 

 

 

 

 

 

Voltage output of the bandgap filter circuit into 41210

 

 

VCCBGPE

Bridge, separated from the rest of the VCC15s. See

2.5V ±3% PCI Express voltage.

 

 

Figure 25 for circuit.

 

 

 

 

 

 

 

Connect to 1.5V power supply.

 

 

 

Decoupling:

 

 

VCCPE

3 0.1uF caps beneath package (backside of board)

1.5V ±3% PCI Express voltage.

 

4 1.0 uF caps as close as design rules permit to

 

 

package

 

 

 

2 10 uF caps as close as design rules permit to

 

 

 

package

 

 

 

 

 

 

VSS

Connect to ground.

Ground reference for all

 

supplies.

 

 

 

 

 

 

 

 

VSSAPE

See Figure 24 for circuit.

Analog ground for PCI Express.

 

 

 

 

 

VSSBGPE

Ground for the bandgap filter circuit, separated from

Ground for analog bandgap

 

the rest of the VSSs. See Figure 25 for circuit.

voltage.

 

 

 

 

 

 

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

63

Image 63
Contents Design Guide Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents Figures Tables Revision HistoryDescription This page intentionally left blank Term Definition About This DocumentTerminology and Definitions Terminology and Definitions Sheet 1Terminology and Definitions Sheet 2 About This DocumentPCI Express Interface Features PCI-X Interface FeaturesIntroduction2 Introduction Power ManagementSMBus for configuration register initialization SMBus InterfaceMicrocontroller Connections to the 41210 Bridge Bridge Microcontroller Block DiagramRelated Documents JtagIntel41210 Serial to Parallel PCI Bridge Applications Intel 41210 Bridge Adapter Card Block DiagramThis page intentionally left blank Package Information Package SpecificationPackage Information Bottom View 41210 Bridge 567-Ball Fcbga Package DimensionsSide View 41210 Bridge 567-Ball Fcbga Package Dimensions This page intentionally left blank 41210 Bridge Decoupling Guidelines Power Plane LayoutPower Plane Layout Bridge Decoupling Guidelines Split Voltage PlanesPCI Bridge Reset and Power Timing Considerations5 ARST#,BRST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Bridge Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI ConsiderationsPower Distribution and Decoupling Trace ImpedanceDecoupling Cross Section of Differential Trace Differential ImpedanceBoard Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout GuidelinesPCI-X Layout Guidelines InterruptsINTx Routing Table Interrupt Binding for Devices Behind a Bridge PCI ArbitrationInterrupt Routing for Devices Behind a Bridge PCI-X Layout GuidelinesPCI Resistor Compensation PCI General Layout GuidelinesPCI-X Signals PCI Pullup Resistors Not RequiredPCI/PCI-X Frequency/Mode Straps BCBE#74, BDEVSEL#, BFRAME#, BINTA#, BINTB#, BINTC#, BINTD# PCI Clock Layout GuidelinesPCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements SummaryPCI-X Slot Guidelines PCI-X Topology Layout GuidelinesEmbedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHzPCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI 66 MHz Embedded TopologyPCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode TopologyThis page intentionally left blank General recommendations PCI Express LayoutAdapter Card Routing Recommendations Sheet 1 PCI-Express Layout GuidelinesAdapter Card Layout Guidelines PCI Express LayoutAdapter Card Routing Recommendations Sheet 2 This page intentionally left blank Config Circuit Implementations10.1 41210 Bridge Analog Voltage Filters PCI Analog Voltage Filters PCI Express Analog Voltage FilterCircuit Implementations Bandgap Analog Voltage Filter VccapeVssape Bandgap Analog Voltage Filter Circuit VccbgpeVSS Vssbgpe PERCOMP0 PERCOMP1 Rcomp Reference and Compensation Circuit ImplementationsSMBUs Address Configuration SM BusBit Value Board Stack-up Bridge Customer Reference BoardsBridge Customer Reference Boards Layer Type Thickness Copper WeightMaterial ImpedanceMechanical Outline of the 41210 Bridge Board OutlineThis page intentionally left blank PERCOMP10 Design Guide ChecklistPCI Express Interface Signals Signals Recommendations Reason/ImpactPCI/PCI-X Interface Signals Design Guide ChecklistBpcixcap AM66ENBM66EN PERST# ApcixcapMiscellaneous Signals SMBus Interface SignalsSignals VCC33 Power and Ground SignalsSignal Recommendations Reason/Impact VCC15Jtag Signals
Related manuals
Manual 120 pages 33.98 Kb