PCI-X Layout Guidelines
Table 6. PCI-X Signals
| A PCI Bus Segment: | |
| A_ACK64#, A_AD[63:0], A_CBE_[7:0]#, A_DEVSEL#, A_FRAME#, | |
| A_GNT_[5:0]#, A_IRDY#, A_LOCK#, A_PAR64, A_REQ64#, A_REQ_[5:0]#, | |
Timing Critical Signals | A_STOP#, A_TRDY#, A_CLKO[6:0], A_CLKI | |
B PCI Bus Segment: | ||
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| B_ACK64#, B_AD[63:0], B_CBE_[7:0]#, B_DEVSEL#, B_FRAME#, | |
| B_GNT_[5:0]#, B_IRDY#, B_LOCK#, B_PAR64, B_REQ64#, B_REQ_[5:0]#, | |
| B_STOP#,B_TRDY#, B_CLKO[6:0], B_CLKI | |
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| A PCI Bus Segment: | |
Reset Signals | A_RST#, A_PME# | |
B PCI Bus Segment: | ||
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| B_RST#, B_PME# | |
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| A PCI Bus Segment: | |
Non Timing Critical | A_133EN, A_IRQ[15:0]#, A_M66EN, A_PCIXCAP, A_PERR#, A_SERR# | |
Signals | B PCI Bus Segment: | |
| B_133EN, B_IRQ[15:0]#, B_M66EN, B_PCIXCAP, B_PERR#, B_SERR# | |
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Table 7. PCI/PCI-X Frequency/Mode Straps
A_PCIXCAP, B_PCIXCAP | A_M66EN, | A_133EN, | Bus | |
B_M66EN | B_133EN | Mode/ | ||
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| (on board) | Freq | |
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0 | 0 | X | PCI 33 | |
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0 | 1 | X | PCI 66 | |
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signal to ground through a 10KΩ | X | X | ||
±5% resistor in parallel with a | ||||
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0.01uF ±10% capacitor. |
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PCIXCAP to ground through a | X | 0 | ||
0.01uF ±10% capacitor. |
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PCIXCAP to ground through a | X | 1 | ||
0.01uF ±10% capacitor. |
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Note: All signals sampled on the rising edge of PERST#.
8.3.1PCI Pullup Resistors Not Required
PCI control signals on the 41210 Bridge do NOT require pullup resistors on the adapter card to ensure that they contain stable values when no agent is actively driving the bus. These include:
A_ACK64#, A_AD[63:32], A_CBE#[7:4], A_DEVSEL#, A_FRAME#, A_INTA#, A_INTB#, A_INTC#, A_INTD#, A_IRDY#, A_PERR#, A_PAR, A_GNT#[5:0], A_REQ#[5:0], A_LOCK#, A_PAR64, A_REQ64#, A_SERR#, A_STOP#, A_TRDY#, B_ACK64#, B_AD[63:32],
34 | Intel® 41210 Serial to Parallel PCI Bridge Design Guide |