Intel 41210 manual Jtag Signals

Page 64

Design Guide Checklist

Table 24. JTAG Signals

	Signal	Recommendations	Reason/Impact

	TCK	If not used for JTAG, leave as No Connect	Internal pull-up

	TDI	If not used for JTAG, leave as No Connect	Internal pull-up

	TDO	If not used for JTAG, leave as No Connect	Internal pull-up

	TMS	If not used for JTAG, leave as No Connect	Internal pull-up

	TRST#	Connect to ground via a 1KΩ pulldown resistor.	If TAP interface is not used this
	TRST#	Connect to ground via a 1KΩ pulldown resistor.	should be tied to ground.
			should be tied to ground.

64	Intel® 41210 Serial to Parallel PCI Bridge Design Guide

Image 64

Contents Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents Figures Revision History TablesDescription This page intentionally left blank About This Document Terminology and DefinitionsTerminology and Definitions Sheet 1 Term DefinitionAbout This Document Terminology and Definitions Sheet 2PCI-X Interface Features PCI Express Interface FeaturesIntroduction2 Power Management SMBus for configuration register initializationSMBus Interface IntroductionBridge Microcontroller Block Diagram Microcontroller Connections to the 41210 BridgeJtag Related DocumentsIntel 41210 Bridge Adapter Card Block Diagram Intel41210 Serial to Parallel PCI Bridge ApplicationsThis page intentionally left blank Package Specification Package InformationBottom View 41210 Bridge 567-Ball Fcbga Package Dimensions Package InformationSide View 41210 Bridge 567-Ball Fcbga Package Dimensions This page intentionally left blank Power Plane Layout 41210 Bridge Decoupling GuidelinesPower Plane Layout Split Voltage Planes Bridge Decoupling GuidelinesPCI ARST#,BRST# and PERST# Timing Requirements Bridge Reset and Power Timing Considerations5VCC15 and VCC33 Voltage Requirements Bridge Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk EMI Considerations General Routing GuidelinesTrace Impedance Power Distribution and DecouplingDecoupling Differential Impedance Cross Section of Differential TraceAdapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Adapter Card StackupInterrupts PCI-X Layout GuidelinesINTx Routing Table PCI Arbitration Interrupt Routing for Devices Behind a BridgePCI-X Layout Guidelines Interrupt Binding for Devices Behind a BridgePCI General Layout Guidelines PCI Resistor CompensationPCI Pullup Resistors Not Required PCI-X SignalsPCI/PCI-X Frequency/Mode Straps PCI Clock Layout Guidelines BCBE#74, BDEVSEL#, BFRAME#, BINTA#, BINTB#, BINTC#, BINTD#PCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing GuidelinesPCI-X Topology Layout Guidelines PCI-X Slot GuidelinesEmbedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 133 MHzParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing RecommendationsPCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing RecommendationsPCI 66 MHz Embedded Topology PCI 66 MHz Embedded TablePCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing RecommendationsThis page intentionally left blank PCI Express Layout General recommendationsPCI-Express Layout Guidelines Adapter Card Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations Config10.1 41210 Bridge Analog Voltage Filters PCI Express Analog Voltage Filter PCI Analog Voltage FiltersCircuit Implementations Vccape Bandgap Analog Voltage FilterVssape Vccbgpe Bandgap Analog Voltage Filter CircuitVSS Vssbgpe Reference and Compensation Circuit Implementations PERCOMP0 PERCOMP1 RcompSM Bus SMBUs Address ConfigurationBit Value Bridge Customer Reference Boards Board Stack-upLayer Type Thickness Copper Weight MaterialImpedance Bridge Customer Reference BoardsBoard Outline Mechanical Outline of the 41210 BridgeThis page intentionally left blank Design Guide Checklist PCI Express Interface SignalsSignals Recommendations Reason/Impact PERCOMP10Design Guide Checklist PCI/PCI-X Interface SignalsAM66EN BM66EN PERST#Apcixcap BpcixcapSMBus Interface Signals Miscellaneous SignalsSignals Power and Ground Signals Signal Recommendations Reason/ImpactVCC15 VCC33Jtag Signals

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