Intel® 5100 MCH Chipset
Revision History
Date | Revision | Description |
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| Added the CompactPCI* reference solution |
July 2008 | 003 | Added Figure 26, Figure 27, and Figure 28 |
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| Updated the supplier information |
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February 2008 | 002 | Updated the TDPMax config value to 25.7 W in Table 3 |
November 2007 | 001 | Initial release |
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Revision Number Descriptions
Revision | Associated Life Cycle Milestone | Release Information | |
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0.0 | POP L3 Closure | Initial Documentation - Typically Internal Only | |
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When Needed | Project Dependent - Typically Internal Only | ||
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0.5 | Design Win Phase | First, Required Customer Release | |
When Needed | Project Dependent | ||
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0.7 | Simulations Complete | Second, Recommended Customer Release | |
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When Needed | Project Dependent | ||
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1.0 | First Silicon Samples | Required Customer Release | |
When Needed | Project Dependent (Recommended) | ||
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1.5 | Qualification Silicon Samples | Project Dependent | |
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When Needed | Project Dependent | ||
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NDA - 2.0 | First SKU Launch | Required Customer Release - Product Launch | |
Public - | |||
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2.1 and up | When Needed | Project Dependent | |
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Note: Rows highlighted in gray are required revisions. |
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Intel® 5100 Memory Controller Hub Chipset for Communications, Embedded, and Storage Applications
July 2008 | TDG |
Order Number: | 5 |