SMC Networks AHB SRAM/NOR manual Incremented, An 8-bit data item, Data bus, Multi-master operation

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Glossary

Boundary scan chain

 

A boundary scan chain is made up of serially-connected devices that implement

 

boundary scan technology using a standard JTAG TAP interface. Each device contains

 

at least one TAP controller containing shift registers that form the chain connected

 

between TDI and TDO, through which test data is shifted. Processors can contain

 

several shift registers to enable you to access selected parts of the device.

Burst

A group of transfers to consecutive addresses. Because the addresses are consecutive,

 

there is no requirement to supply an address for any of the transfers after the first one.

 

This increases the speed at which the group of transfers can occur. Bursts over AMBA

 

are controlled using signals to indicate the length of the burst and how the addresses are

 

incremented.

 

See also Beat.

Byte

An 8-bit data item.

Byte lane strobe

A signal that is used for unaligned or mixed-endian data accesses to determine the byte

 

lanes that are active in a transfer. One bit of this signal corresponds to eight bits of the

 

data bus.

Multi-master AHB

Typically a shared, not multi-layer, AHB interconnect scheme. More than one master

 

connects to a single AMBA AHB link. In this case, the bus is implemented with a set of

 

full AMBA AHB master interfaces. Masters that use the AMBA AHB-Lite protocol

 

must connect through a wrapper to supply full AMBA AHB master signals to support

 

multi-master operation.

Endianness

Byte ordering. The scheme that determines the order that successive bytes of a data

 

word are stored in memory. An aspect of the system’s memory mapping.

 

See also Little-endian and Big-endian

Little-endian

Byte ordering scheme in which bytes of increasing significance in a data word are stored

 

at increasing addresses in memory.

 

See also Big-endian and Endianness.

Little-endian memory

 

 

 

Memory in which:

 

•

a byte or halfword at a word-aligned address is the least significant byte or

 

 

halfword within the word at that address

 

•

a byte at a halfword-aligned address is the least significant byte within the

 

 

halfword at that address.

See also Big-endian memory.

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

Glossary-3

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Contents PrimeCell AHB SRAM/NOR Memory Controller PL241 Copyright 2006 ARM Limited. All rights reserved PrimeCell AHB SRAM/NOR Memory Controller PL241Technical Reference Manual Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Feedback on PrefaceIntended audience Using this manualAbout this manual Product revision statusBold ConventionsTypographical Signals Timing diagramsARM publications NumberingFurther reading Feedback on this manual FeedbackFeedback on this product Introduction SMC on About the AHB MCThis section describes AHB to APB bridge AHB interfaceClock domains Low-power interfaces3 SMC Intel W18 series NOR FLASH, for example 28f128W18td Supported devicesIntroduction Copyright 2006 ARM Limited. All rights reserved Functional Overview This section is divided into Functional descriptionStatic memory clock domain Smcmreset0nLow-power interface AHB clock domainInterrupts on SMCMain blocks of the SMC are Format onMemory manager SMC interfaceAPB slave interface FormatInterrupts Pad interfaceAHB fixed burst types Functional operationAHB interface operation Broken bursts Bufferable bit of the Hprot signalUndefined length Incr bursts Locked transfers AHB response signalsRead after write hazard detection buffer AHB to APB bridge operation Big-endian 32-bit modeRemoval of AHB error response logic Registered HwdataAhbc memory map Clock domain operationStatic memory clocking options Low-power interface operationStatic memory clocking options 1lists the static memory clocking optionsAn active output Domaincactive Where Domain is ahb or smcAccepting requests SMC states are as follows SMC functional operationOperating states Clocking Clocking and resetsResets Smcagtm0sync Miscellaneous signalsSmcuserconfig70 Smcuserstatus70Hazard handling APB slave interface operationFormat block Sram memory accesses Memory burst length Memory manager operation Low-power operationChip configuration registers 11 Chip configuration registers Software mechanism Direct commandsDevice pin mechanism 12 Device pin mechanism 13 Software mechanism Memory interface operation Sram timing tables and diagramsInterrupts operation Asynchronous read Sram cycles register settings Asynchronous read opmode chip register settings14 Asynchronous read 4and -5list the smcopmode00-3 and Sram Register settingsAsynchronous write Sram cycles register settings 6and -7list the smcopmode00-3 and Sram Register settingsAsynchronous write opmode chip register settings 10 Page read opmode chip register settings 8and -9list the smcopmode00-3 and Sram Register settings10and -11list the smcopmode00-3 and Sram Register settings 13 Synchronous burst read Sram cycles register settings 12and -13list the smcopmode00-3 and Sram Register settings12 Synchronous burst read opmode chip register settings 19 Synchronous burst read 20 Synchronous burst read in multiplexed-mode 14and -15list the smcopmode00-3 and Sram Register settings17 Synchronous burst write Sram cycles register settings 16and -17list the smcopmode00-3 and Sram Register settings16 Synchronous burst write opmode chip register settings 22 Synchronous burst write in multiplexed-mode 18and -19list the smcopmode00-3 and Sram Register settingsB0100 B0110 B001 20and -21list the smcopmode00-3 and Sram Register settingsTCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model Register summary 2shows the SMC configuration register map1lists the SMC Registers Name Base offset Type Reset value DescriptionRegister summary 2lists the register bit assignments Register descriptionsThis section describes the SMC registers SMC Memory Controller Status Register atBits Name Function SMC Memory Interface Configuration Register at3lists the register bit assignments Smcmemccfgset Register bit assignments SMC Set Configuration Register atSmcmemccfgclr Register bit assignments Bits Name Function SMC Clear Configuration Register at 0x100C4lists the register bit assignments 5lists the register bit assignmentsSmcdirectcmd Register bit assignments SMC Direct Command Register at6lists the register bit assignments Lists the register bit assignments SMC Set Cycles Register at12 smcsetopmode Register bit assignments SMC Set Opmode Register at8lists the register bit assignments Memory width mw field Smcsetopmode Register bit assignmentsSmcrefreshperiod0 Register bit assignments SMC Refresh Period 0 Register atSMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140 SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 10lists the register bit assignments11lists the register bit assignments 12 smcuserstatus Register bit assignments SMC User Status Register at12lists the register bit assignments 11 smcopmode Register bit assignmentsBits Name Description SMC User Configuration Register at13 smcuserconfig Register bit assignments 13 lists the register bit assignments15 smcperiphid0 Register bit assignments Bits Name Function Following section describe the smcperiphid RegistersSMC Peripheral Identification Register 17 smcperiphid2 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function19shows the register bit assignments SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC20 smcpcellid0 Register bit assignments Bits Name Function These registers cannot be read in the Reset stateFollowing sections describe the smcpcellid Registers SMC PrimeCell Identification Register23 smcpcellid3 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name FunctionProgrammer’s Model for Test Lists the SMC integration test registers Test registers are provided for integration testingSMC Integration Configuration Register at 0x1E00 SMC integration test registersSmcintinputs Register bit assignments Bits Name Function Integration Inputs Register at 0x1E04State Integration Outputs Register at 0x1E08Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 SMC and memory initialization sheet 3 Where = denotes the appropriate chip selectARM DDI 0389B Signal Descriptions Where Ahbc = AHB Configuration signals About the signals listName Type Source Description Destination Clocks and resetsTable A-1lists the clock and reset signals Table A-2 AHB signals AHB signalsTable A-2lists the AHB signals Where = 0 or C, where C = ConfigurationTable A-3lists the SMC memory interface signals SMC memory interface signalsTable A-4 SMC miscellaneous signals SMC miscellaneous signalsTable A-4lists the SMC miscellaneous signals Table A-5lists the low-power interface signals Low-power interfaceName Source Description Type Destination Configuration signalTable A-6lists the configuration signal Table A-6 Configuration signalScan chains Table A-7lists the scan chain signalsTable A-7 Scan chain signals ARM DDI 0389B Advanced Microcontroller Bus Architecture Amba Advanced High-performance Bus AHBAdvanced Peripheral Bus APB See also Little-endian memoryMulti-master operation IncrementedAn 8-bit data item Data busOther purposes Divisible by fourSee Unpredictable That event resource is UnpredictableReserved Has been completedWritten as 0 and read as RemappingGlossary-6
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