SMC Networks PL241, AHB SRAM/NOR manual Undefined length Incr bursts, Broken bursts

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Functional Overview

Undefined length INCR bursts

All undefined length INCR bursts are converted to INCR bursts of length four. Many AHB masters rely on using undefined length INCR bursts to access data. If each INCR transfer is processed as a single transfer by the internal protocol then the performance is significantly degraded.

The bridge converts the incoming INCR transfers to INCR transfers of length four, INCR4. This mean that the bridge speculatively requests data from the internal interconnect, before it knows it is going to require it. If the AHB master continues the burst, then the data can be returned quickly because it has already been requested. When the INCR burst finishes, the bridge disregards any data requested from the internal interconnect that is not required.

Any INCR burst of less than four beats results in a broken INCR4. Undefined length INCR bursts of more than four beats are split into an appropriate number of INCR4s plus a broken INCR4, if required.

Broken bursts

To fully support the AMBA AHB 2.0 specification, the bridge supports all broken AHB bursts. Although bursts cannot be broken by an AHB master, if the AHB system has multiple masters then the AHB system arbitration can break a burst. Also, because the bridge converts INCR to INCR4, broken INCR4s occur when undefined length INCRs of a length not equal to a multiple of four are performed.

To support broken bursts, the bridge must keep track of how many beats of a burst have been performed and ensure it obeys the protocol of the interconnect. For read bursts, this means draining the interconnect of any requested data that is not required. For write bursts this means artificially extending write data with enough beats to obey the protocol. The interconnect uses write strobes to indicate the bytes of the data bus that are valid. When extending broken bursts, these strobes are deasserted so that the artificial data does not corrupt the actual memory.

Bufferable bit of the HPROT signal

The bufferable bit of the HPROT signal determines whether the bridge must wait for a write transfer to complete internally. The AHB protection control bits support the concept of bufferable data accesses. The HPROT[2] signal determines this. The internal interconnect supports the concept of a write response to indicate when data has actually been written to memory. The bridge exploits these features by not waiting for the write response if the access is described as bufferable. This enables numerous bufferable writes to occur with minimum latency. These are accepted by the interconnect and queued in the memory controller.

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Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

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Contents PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference Manual PrimeCell AHB SRAM/NOR Memory Controller PL241Copyright 2006 ARM Limited. All rights reserved Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Preface Feedback onUsing this manual About this manualProduct revision status Intended audienceTypographical ConventionsBold Timing diagrams SignalsFurther reading NumberingARM publications Feedback on this product FeedbackFeedback on this manual Introduction This section describes About the AHB MCSMC on AHB interface AHB to APB bridge3 SMC Low-power interfacesClock domains Supported devices Intel W18 series NOR FLASH, for example 28f128W18tdIntroduction Copyright 2006 ARM Limited. All rights reserved Functional Overview Functional description This section is divided intoSmcmreset0n Low-power interfaceAHB clock domain Static memory clock domainSMC Main blocks of the SMC areFormat on Interrupts onSMC interface APB slave interfaceFormat Memory managerPad interface InterruptsAHB interface operation Functional operationAHB fixed burst types Undefined length Incr bursts Bufferable bit of the Hprot signalBroken bursts Read after write hazard detection buffer AHB response signalsLocked transfers Big-endian 32-bit mode Removal of AHB error response logicRegistered Hwdata AHB to APB bridge operationClock domain operation Ahbc memory mapLow-power interface operation Static memory clocking options1lists the static memory clocking options Static memory clocking optionsWhere Domain is ahb or smc An active output DomaincactiveAccepting requests Operating states SMC functional operationSMC states are as follows Clocking and resets ClockingResets Miscellaneous signals Smcuserconfig70Smcuserstatus70 Smcagtm0syncFormat block APB slave interface operationHazard handling Sram memory accesses Memory burst length Chip configuration registers Low-power operationMemory manager operation 11 Chip configuration registers Device pin mechanism Direct commandsSoftware mechanism 12 Device pin mechanism 13 Software mechanism Interrupts operation Sram timing tables and diagramsMemory interface operation Asynchronous read opmode chip register settings Asynchronous read Sram cycles register settings4and -5list the smcopmode00-3 and Sram Register settings 14 Asynchronous readAsynchronous write opmode chip register settings 6and -7list the smcopmode00-3 and Sram Register settingsAsynchronous write Sram cycles register settings 10and -11list the smcopmode00-3 and Sram Register settings 8and -9list the smcopmode00-3 and Sram Register settings10 Page read opmode chip register settings 12 Synchronous burst read opmode chip register settings 12and -13list the smcopmode00-3 and Sram Register settings13 Synchronous burst read Sram cycles register settings 19 Synchronous burst read 14and -15list the smcopmode00-3 and Sram Register settings 20 Synchronous burst read in multiplexed-mode16 Synchronous burst write opmode chip register settings 16and -17list the smcopmode00-3 and Sram Register settings17 Synchronous burst write Sram cycles register settings 18and -19list the smcopmode00-3 and Sram Register settings 22 Synchronous burst write in multiplexed-mode20and -21list the smcopmode00-3 and Sram Register settings B0100 B0110 B001TCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model 2shows the SMC configuration register map Register summaryName Base offset Type Reset value Description 1lists the SMC RegistersRegister summary Register descriptions This section describes the SMC registersSMC Memory Controller Status Register at 2lists the register bit assignments3lists the register bit assignments SMC Memory Interface Configuration Register atBits Name Function SMC Set Configuration Register at Smcmemccfgset Register bit assignmentsSMC Clear Configuration Register at 0x100C 4lists the register bit assignments5lists the register bit assignments Smcmemccfgclr Register bit assignments Bits Name Function6lists the register bit assignments SMC Direct Command Register atSmcdirectcmd Register bit assignments SMC Set Cycles Register at Lists the register bit assignmentsSMC Set Opmode Register at 12 smcsetopmode Register bit assignments8lists the register bit assignments Smcsetopmode Register bit assignments Memory width mw fieldSMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140 SMC Refresh Period 0 Register atSmcrefreshperiod0 Register bit assignments 10lists the register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x114411lists the register bit assignments SMC User Status Register at 12lists the register bit assignments11 smcopmode Register bit assignments 12 smcuserstatus Register bit assignmentsSMC User Configuration Register at 13 smcuserconfig Register bit assignments13 lists the register bit assignments Bits Name DescriptionSMC Peripheral Identification Register Following section describe the smcperiphid Registers15 smcperiphid0 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name FunctionSMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC 19shows the register bit assignmentsThese registers cannot be read in the Reset state Following sections describe the smcpcellid RegistersSMC PrimeCell Identification Register 20 smcpcellid0 Register bit assignments Bits Name Function22 smcpcellid2 Register bit assignments Bits Name Function 23 smcpcellid3 Register bit assignments Bits Name FunctionProgrammer’s Model for Test Test registers are provided for integration testing SMC Integration Configuration Register at 0x1E00SMC integration test registers Lists the SMC integration test registersIntegration Inputs Register at 0x1E04 Smcintinputs Register bit assignments Bits Name FunctionIntegration Outputs Register at 0x1E08 StateDevice Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 Where = denotes the appropriate chip select SMC and memory initialization sheet 3ARM DDI 0389B Signal Descriptions About the signals list Where Ahbc = AHB Configuration signalsTable A-1lists the clock and reset signals Clocks and resetsName Type Source Description Destination AHB signals Table A-2lists the AHB signalsWhere = 0 or C, where C = Configuration Table A-2 AHB signalsSMC memory interface signals Table A-3lists the SMC memory interface signalsTable A-4lists the SMC miscellaneous signals SMC miscellaneous signalsTable A-4 SMC miscellaneous signals Low-power interface Table A-5lists the low-power interface signalsConfiguration signal Table A-6lists the configuration signalTable A-6 Configuration signal Name Source Description Type DestinationTable A-7 Scan chain signals Table A-7lists the scan chain signalsScan chains ARM DDI 0389B Advanced High-performance Bus AHB Advanced Microcontroller Bus Architecture AmbaSee also Little-endian memory Advanced Peripheral Bus APBIncremented An 8-bit data itemData bus Multi-master operationDivisible by four See UnpredictableThat event resource is Unpredictable Other purposesHas been completed Written as 0 and read asRemapping ReservedGlossary-6
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