SMC Networks AHB SRAM/NOR, PL241 manual An active output Domaincactive, Where Domain is ahb or smc

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Functional Overview

an active output

<domain>_cactive

Where:

<domain> is ahb or smc.

Figure 2-7explains the protocol for the interface by showing a request to enter low-power mode.

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7

7

KFON

DKEBFV\VUHT

DKEBFV\VDFN

DKEBFDFWLYH

Figure 2-7 Request to enter low-power mode

The memory controller receives a request to enter low-power mode, indicated by <domain>_csysreq being driven LOW by the system clock controller, as shown at T1. The memory controller then has the chance to perform any required operations to prepare for the clock to be switched off. The memory controller acknowledges the request by asserting <domain>_csysack LOW, as shown at T2. At this point the <domain>_cactive signal is used to indicate whether the request has been accepted or denied. If the request is accepted, <domain>_cactive is LOW, as shown in Figure 2-7.If the request is denied, <domain>_cactive is HIGH. If the request is accepted, then the clock to that domain can be switched off. The peripheral is brought out of low-power state by restarting the clock and driving <domain>_csysreq HIGH, as shown at T4. The memory controller completes the handshake by driving <domain>_csysack HIGH, as shown at T5. Figure 2-8shows the AHB domain denying a low-power request.

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7

7

KFON

DKEBFV\VUHT

DKEBFV\VDFN

DKEBFDFWLYH

Figure 2-8 AHB domain denying a low-power request

When ahb_csysack is asserted LOW, the ahb_cactive signal is HIGH, as shown at T3, indicating the AHB domain is busy and the clock cannot be switched off. The handshake must be completed.

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

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Contents PrimeCell AHB SRAM/NOR Memory Controller PL241 PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference ManualCopyright 2006 ARM Limited. All rights reserved Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Feedback on PrefaceAbout this manual Using this manualProduct revision status Intended audienceConventions TypographicalBold Signals Timing diagramsNumbering Further readingARM publications Feedback Feedback on this productFeedback on this manual Introduction About the AHB MC This section describesSMC on AHB to APB bridge AHB interfaceLow-power interfaces 3 SMCClock domains Intel W18 series NOR FLASH, for example 28f128W18td Supported devicesIntroduction Copyright 2006 ARM Limited. All rights reserved Functional Overview This section is divided into Functional descriptionLow-power interface Smcmreset0nAHB clock domain Static memory clock domainMain blocks of the SMC are SMCFormat on Interrupts onAPB slave interface SMC interfaceFormat Memory managerInterrupts Pad interfaceFunctional operation AHB interface operationAHB fixed burst types Bufferable bit of the Hprot signal Undefined length Incr burstsBroken bursts AHB response signals Read after write hazard detection bufferLocked transfers Removal of AHB error response logic Big-endian 32-bit modeRegistered Hwdata AHB to APB bridge operationAhbc memory map Clock domain operationStatic memory clocking options Low-power interface operation1lists the static memory clocking options Static memory clocking optionsAn active output Domaincactive Where Domain is ahb or smcAccepting requests SMC functional operation Operating statesSMC states are as follows Clocking Clocking and resetsResets Smcuserconfig70 Miscellaneous signalsSmcuserstatus70 Smcagtm0syncAPB slave interface operation Format blockHazard handling Sram memory accesses Memory burst length Low-power operation Chip configuration registersMemory manager operation 11 Chip configuration registers Direct commands Device pin mechanismSoftware mechanism 12 Device pin mechanism 13 Software mechanism Sram timing tables and diagrams Interrupts operationMemory interface operation Asynchronous read Sram cycles register settings Asynchronous read opmode chip register settings14 Asynchronous read 4and -5list the smcopmode00-3 and Sram Register settings6and -7list the smcopmode00-3 and Sram Register settings Asynchronous write opmode chip register settingsAsynchronous write Sram cycles register settings 8and -9list the smcopmode00-3 and Sram Register settings 10and -11list the smcopmode00-3 and Sram Register settings10 Page read opmode chip register settings 12and -13list the smcopmode00-3 and Sram Register settings 12 Synchronous burst read opmode chip register settings13 Synchronous burst read Sram cycles register settings 19 Synchronous burst read 20 Synchronous burst read in multiplexed-mode 14and -15list the smcopmode00-3 and Sram Register settings16and -17list the smcopmode00-3 and Sram Register settings 16 Synchronous burst write opmode chip register settings17 Synchronous burst write Sram cycles register settings 22 Synchronous burst write in multiplexed-mode 18and -19list the smcopmode00-3 and Sram Register settingsB0100 B0110 B001 20and -21list the smcopmode00-3 and Sram Register settingsTCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model Register summary 2shows the SMC configuration register map1lists the SMC Registers Name Base offset Type Reset value DescriptionRegister summary This section describes the SMC registers Register descriptionsSMC Memory Controller Status Register at 2lists the register bit assignmentsSMC Memory Interface Configuration Register at 3lists the register bit assignmentsBits Name Function Smcmemccfgset Register bit assignments SMC Set Configuration Register at4lists the register bit assignments SMC Clear Configuration Register at 0x100C5lists the register bit assignments Smcmemccfgclr Register bit assignments Bits Name FunctionSMC Direct Command Register at 6lists the register bit assignmentsSmcdirectcmd Register bit assignments Lists the register bit assignments SMC Set Cycles Register at12 smcsetopmode Register bit assignments SMC Set Opmode Register at8lists the register bit assignments Memory width mw field Smcsetopmode Register bit assignmentsSMC Refresh Period 0 Register at SMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140Smcrefreshperiod0 Register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 10lists the register bit assignments11lists the register bit assignments 12lists the register bit assignments SMC User Status Register at11 smcopmode Register bit assignments 12 smcuserstatus Register bit assignments13 smcuserconfig Register bit assignments SMC User Configuration Register at13 lists the register bit assignments Bits Name DescriptionFollowing section describe the smcperiphid Registers SMC Peripheral Identification Register15 smcperiphid0 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function19shows the register bit assignments SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFCFollowing sections describe the smcpcellid Registers These registers cannot be read in the Reset stateSMC PrimeCell Identification Register 20 smcpcellid0 Register bit assignments Bits Name Function23 smcpcellid3 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name FunctionProgrammer’s Model for Test SMC Integration Configuration Register at 0x1E00 Test registers are provided for integration testingSMC integration test registers Lists the SMC integration test registersSmcintinputs Register bit assignments Bits Name Function Integration Inputs Register at 0x1E04State Integration Outputs Register at 0x1E08Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 SMC and memory initialization sheet 3 Where = denotes the appropriate chip selectARM DDI 0389B Signal Descriptions Where Ahbc = AHB Configuration signals About the signals listClocks and resets Table A-1lists the clock and reset signalsName Type Source Description Destination Table A-2lists the AHB signals AHB signalsWhere = 0 or C, where C = Configuration Table A-2 AHB signalsTable A-3lists the SMC memory interface signals SMC memory interface signalsSMC miscellaneous signals Table A-4lists the SMC miscellaneous signalsTable A-4 SMC miscellaneous signals Table A-5lists the low-power interface signals Low-power interfaceTable A-6lists the configuration signal Configuration signalTable A-6 Configuration signal Name Source Description Type DestinationTable A-7lists the scan chain signals Table A-7 Scan chain signalsScan chains ARM DDI 0389B Advanced Microcontroller Bus Architecture Amba Advanced High-performance Bus AHBAdvanced Peripheral Bus APB See also Little-endian memoryAn 8-bit data item IncrementedData bus Multi-master operationSee Unpredictable Divisible by fourThat event resource is Unpredictable Other purposesWritten as 0 and read as Has been completedRemapping ReservedGlossary-6