SMC Networks PL241 Memory manager operation, Low-power operation, Chip configuration registers

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Functional Overview

2.4.6Memory manager operation

The memory manager module is responsible for controlling the state of the SMC and the updating of chip configuration registers.

This subsection describes:

•Low-power operation

•Chip configuration registers

•Direct commands on page 2-24.

Low-power operation

The SMC accepts requests to enter the Low-power state through either the SMC low-power interface or the APB register interface.

The SMC does not enter the power-down state until it has received an idle indication from all areas of the peripheral, that is:

•there is no valid transfer held in the Format block

•there are no valid transfers held in the SMC interface

•all FIFOs are empty

•all memory interface blocks are IDLE.

When the Low-power state is entered, no new memory transfers are accepted until the SMC has been moved out of Low-power state. The SMC does not request to move out of Low-power state, and never refuses a power-down request.

Chip configuration registers

The SMC provides a mechanism for synchronizing the switching of operating modes of the SMC with that of the memory device.

The smc_set_cycles Register and smc_set_opmode Register act as holding registers for new operating parameters until the SMC detects the memory device has switched modes.

Figure 2-11 on page 2-23shows the memory manager containing a bank of registers for each memory chip supported by the SMC. The manager register bank consists of all the timing parameters smc_sram_cycles0_<0-3> and smc_opmode0_<0-3>, that are required for the controller to correctly time any type of access to a supported memory type.

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Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

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Contents PrimeCell AHB SRAM/NOR Memory Controller PL241 PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference ManualCopyright 2006 ARM Limited. All rights reserved Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Preface Feedback onProduct revision status Using this manualAbout this manual Intended audienceConventions TypographicalBold Timing diagrams SignalsNumbering Further readingARM publications Feedback Feedback on this productFeedback on this manual Introduction About the AHB MC This section describesSMC on AHB interface AHB to APB bridgeLow-power interfaces 3 SMCClock domains Supported devices Intel W18 series NOR FLASH, for example 28f128W18tdIntroduction Copyright 2006 ARM Limited. All rights reserved Functional Overview Functional description This section is divided intoAHB clock domain Smcmreset0nLow-power interface Static memory clock domainFormat on SMCMain blocks of the SMC are Interrupts onFormat SMC interfaceAPB slave interface Memory managerPad interface InterruptsFunctional operation AHB interface operationAHB fixed burst types Bufferable bit of the Hprot signal Undefined length Incr burstsBroken bursts AHB response signals Read after write hazard detection bufferLocked transfers Registered Hwdata Big-endian 32-bit modeRemoval of AHB error response logic AHB to APB bridge operationClock domain operation Ahbc memory map1lists the static memory clocking options Low-power interface operationStatic memory clocking options Static memory clocking optionsWhere Domain is ahb or smc An active output DomaincactiveAccepting requests SMC functional operation Operating statesSMC states are as follows Clocking and resets ClockingResets Smcuserstatus70 Miscellaneous signalsSmcuserconfig70 Smcagtm0syncAPB slave interface operation Format blockHazard handling Sram memory accesses Memory burst length Low-power operation Chip configuration registersMemory manager operation 11 Chip configuration registers Direct commands Device pin mechanismSoftware mechanism 12 Device pin mechanism 13 Software mechanism Sram timing tables and diagrams Interrupts operationMemory interface operation Asynchronous read opmode chip register settings Asynchronous read Sram cycles register settings4and -5list the smcopmode00-3 and Sram Register settings 14 Asynchronous read6and -7list the smcopmode00-3 and Sram Register settings Asynchronous write opmode chip register settingsAsynchronous write Sram cycles register settings 8and -9list the smcopmode00-3 and Sram Register settings 10and -11list the smcopmode00-3 and Sram Register settings10 Page read opmode chip register settings 12and -13list the smcopmode00-3 and Sram Register settings 12 Synchronous burst read opmode chip register settings13 Synchronous burst read Sram cycles register settings 19 Synchronous burst read 14and -15list the smcopmode00-3 and Sram Register settings 20 Synchronous burst read in multiplexed-mode16and -17list the smcopmode00-3 and Sram Register settings 16 Synchronous burst write opmode chip register settings17 Synchronous burst write Sram cycles register settings 18and -19list the smcopmode00-3 and Sram Register settings 22 Synchronous burst write in multiplexed-mode20and -21list the smcopmode00-3 and Sram Register settings B0100 B0110 B001TCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model 2shows the SMC configuration register map Register summaryName Base offset Type Reset value Description 1lists the SMC RegistersRegister summary SMC Memory Controller Status Register at Register descriptionsThis section describes the SMC registers 2lists the register bit assignmentsSMC Memory Interface Configuration Register at 3lists the register bit assignmentsBits Name Function SMC Set Configuration Register at Smcmemccfgset Register bit assignments5lists the register bit assignments SMC Clear Configuration Register at 0x100C4lists the register bit assignments Smcmemccfgclr Register bit assignments Bits Name FunctionSMC Direct Command Register at 6lists the register bit assignmentsSmcdirectcmd Register bit assignments SMC Set Cycles Register at Lists the register bit assignmentsSMC Set Opmode Register at 12 smcsetopmode Register bit assignments8lists the register bit assignments Smcsetopmode Register bit assignments Memory width mw fieldSMC Refresh Period 0 Register at SMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140Smcrefreshperiod0 Register bit assignments 10lists the register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x114411lists the register bit assignments 11 smcopmode Register bit assignments SMC User Status Register at12lists the register bit assignments 12 smcuserstatus Register bit assignments13 lists the register bit assignments SMC User Configuration Register at13 smcuserconfig Register bit assignments Bits Name DescriptionFollowing section describe the smcperiphid Registers SMC Peripheral Identification Register15 smcperiphid0 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name FunctionSMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC 19shows the register bit assignmentsSMC PrimeCell Identification Register These registers cannot be read in the Reset stateFollowing sections describe the smcpcellid Registers 20 smcpcellid0 Register bit assignments Bits Name Function22 smcpcellid2 Register bit assignments Bits Name Function 23 smcpcellid3 Register bit assignments Bits Name FunctionProgrammer’s Model for Test SMC integration test registers Test registers are provided for integration testingSMC Integration Configuration Register at 0x1E00 Lists the SMC integration test registersIntegration Inputs Register at 0x1E04 Smcintinputs Register bit assignments Bits Name FunctionIntegration Outputs Register at 0x1E08 StateDevice Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 Where = denotes the appropriate chip select SMC and memory initialization sheet 3ARM DDI 0389B Signal Descriptions About the signals list Where Ahbc = AHB Configuration signalsClocks and resets Table A-1lists the clock and reset signalsName Type Source Description Destination Where = 0 or C, where C = Configuration AHB signalsTable A-2lists the AHB signals Table A-2 AHB signalsSMC memory interface signals Table A-3lists the SMC memory interface signalsSMC miscellaneous signals Table A-4lists the SMC miscellaneous signalsTable A-4 SMC miscellaneous signals Low-power interface Table A-5lists the low-power interface signalsTable A-6 Configuration signal Configuration signalTable A-6lists the configuration signal Name Source Description Type DestinationTable A-7lists the scan chain signals Table A-7 Scan chain signalsScan chains ARM DDI 0389B Advanced High-performance Bus AHB Advanced Microcontroller Bus Architecture AmbaSee also Little-endian memory Advanced Peripheral Bus APBData bus IncrementedAn 8-bit data item Multi-master operationThat event resource is Unpredictable Divisible by fourSee Unpredictable Other purposesRemapping Has been completedWritten as 0 and read as ReservedGlossary-6