SMC Networks AHB SRAM/NOR, PL241 manual 4and -5list the smcopmode00-3 and Sram Register settings

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Functional Overview

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Figure 2-14 Asynchronous read

Asynchronous read in multiplexed-mode

Table 2-4and Table 2-5list the smc_opmode0_<0-3> and SRAM Register settings.

Table 2-4 Asynchronous read in multiplexed-mode opmode chip register settings

Field	mw	rd_sync	rd_bl	wr_sync	wr_bl	baa	adv	bls	ba

Value	-	b0	b000	-	-	-	b1	-	-

Table 2-5 Asynchronous read in multiplexed-mode SRAM cycles register settings

Field	t_rc	t_wc	t_ceoe	t_wp	t_pc	t_tr

Value	b0111	-	b101	-	-	-

Figure 2-15shows a single asynchronous read transfer in multiplexed-SRAM mode, with tRC = 7, and tCEOE = 5.

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Figure 2-15 Asynchronous read in multiplexed-mode

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

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Contents PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference Manual PrimeCell AHB SRAM/NOR Memory Controller PL241Copyright 2006 ARM Limited. All rights reserved Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Feedback on PrefaceAbout this manual Using this manualProduct revision status Intended audienceTypographical ConventionsBold Signals Timing diagramsFurther reading NumberingARM publications Feedback on this product FeedbackFeedback on this manual Introduction This section describes About the AHB MCSMC on AHB to APB bridge AHB interface3 SMC Low-power interfacesClock domains Intel W18 series NOR FLASH, for example 28f128W18td Supported devicesIntroduction Copyright 2006 ARM Limited. All rights reserved Functional Overview This section is divided into Functional descriptionLow-power interface Smcmreset0nAHB clock domain Static memory clock domainMain blocks of the SMC are SMCFormat on Interrupts onAPB slave interface SMC interfaceFormat Memory managerInterrupts Pad interfaceAHB interface operation Functional operationAHB fixed burst types Undefined length Incr bursts Bufferable bit of the Hprot signalBroken bursts Read after write hazard detection buffer AHB response signalsLocked transfers Removal of AHB error response logic Big-endian 32-bit modeRegistered Hwdata AHB to APB bridge operationAhbc memory map Clock domain operationStatic memory clocking options Low-power interface operation1lists the static memory clocking options Static memory clocking optionsAn active output Domaincactive Where Domain is ahb or smcAccepting requests Operating states SMC functional operationSMC states are as follows Clocking Clocking and resetsResets Smcuserconfig70 Miscellaneous signalsSmcuserstatus70 Smcagtm0syncFormat block APB slave interface operationHazard handling Sram memory accesses Memory burst length Chip configuration registers Low-power operationMemory manager operation 11 Chip configuration registers Device pin mechanism Direct commandsSoftware mechanism 12 Device pin mechanism 13 Software mechanism Interrupts operation Sram timing tables and diagramsMemory interface operation Asynchronous read Sram cycles register settings Asynchronous read opmode chip register settings14 Asynchronous read 4and -5list the smcopmode00-3 and Sram Register settingsAsynchronous write opmode chip register settings 6and -7list the smcopmode00-3 and Sram Register settingsAsynchronous write Sram cycles register settings 10and -11list the smcopmode00-3 and Sram Register settings 8and -9list the smcopmode00-3 and Sram Register settings10 Page read opmode chip register settings 12 Synchronous burst read opmode chip register settings 12and -13list the smcopmode00-3 and Sram Register settings13 Synchronous burst read Sram cycles register settings 19 Synchronous burst read 20 Synchronous burst read in multiplexed-mode 14and -15list the smcopmode00-3 and Sram Register settings16 Synchronous burst write opmode chip register settings 16and -17list the smcopmode00-3 and Sram Register settings17 Synchronous burst write Sram cycles register settings 22 Synchronous burst write in multiplexed-mode 18and -19list the smcopmode00-3 and Sram Register settingsB0100 B0110 B001 20and -21list the smcopmode00-3 and Sram Register settingsTCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model Register summary 2shows the SMC configuration register map1lists the SMC Registers Name Base offset Type Reset value DescriptionRegister summary This section describes the SMC registers Register descriptionsSMC Memory Controller Status Register at 2lists the register bit assignments3lists the register bit assignments SMC Memory Interface Configuration Register atBits Name Function Smcmemccfgset Register bit assignments SMC Set Configuration Register at4lists the register bit assignments SMC Clear Configuration Register at 0x100C5lists the register bit assignments Smcmemccfgclr Register bit assignments Bits Name Function6lists the register bit assignments SMC Direct Command Register atSmcdirectcmd Register bit assignments Lists the register bit assignments SMC Set Cycles Register at12 smcsetopmode Register bit assignments SMC Set Opmode Register at8lists the register bit assignments Memory width mw field Smcsetopmode Register bit assignmentsSMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140 SMC Refresh Period 0 Register atSmcrefreshperiod0 Register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 10lists the register bit assignments11lists the register bit assignments 12lists the register bit assignments SMC User Status Register at11 smcopmode Register bit assignments 12 smcuserstatus Register bit assignments13 smcuserconfig Register bit assignments SMC User Configuration Register at13 lists the register bit assignments Bits Name DescriptionSMC Peripheral Identification Register Following section describe the smcperiphid Registers15 smcperiphid0 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function19shows the register bit assignments SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFCFollowing sections describe the smcpcellid Registers These registers cannot be read in the Reset stateSMC PrimeCell Identification Register 20 smcpcellid0 Register bit assignments Bits Name Function23 smcpcellid3 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name FunctionProgrammer’s Model for Test SMC Integration Configuration Register at 0x1E00 Test registers are provided for integration testingSMC integration test registers Lists the SMC integration test registersSmcintinputs Register bit assignments Bits Name Function Integration Inputs Register at 0x1E04State Integration Outputs Register at 0x1E08Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 SMC and memory initialization sheet 3 Where = denotes the appropriate chip selectARM DDI 0389B Signal Descriptions Where Ahbc = AHB Configuration signals About the signals listTable A-1lists the clock and reset signals Clocks and resetsName Type Source Description Destination Table A-2lists the AHB signals AHB signalsWhere = 0 or C, where C = Configuration Table A-2 AHB signalsTable A-3lists the SMC memory interface signals SMC memory interface signalsTable A-4lists the SMC miscellaneous signals SMC miscellaneous signalsTable A-4 SMC miscellaneous signals Table A-5lists the low-power interface signals Low-power interfaceTable A-6lists the configuration signal Configuration signalTable A-6 Configuration signal Name Source Description Type DestinationTable A-7 Scan chain signals Table A-7lists the scan chain signalsScan chains ARM DDI 0389B Advanced Microcontroller Bus Architecture Amba Advanced High-performance Bus AHBAdvanced Peripheral Bus APB See also Little-endian memoryAn 8-bit data item IncrementedData bus Multi-master operationSee Unpredictable Divisible by fourThat event resource is Unpredictable Other purposesWritten as 0 and read as Has been completedRemapping ReservedGlossary-6