
Functional Overview
Asynchronous write in
Table 2-8 and Table 2-9 list the smc_opmode0_<0-3> and SRAM Register settings.
Table
Field | mw | rd_sync | rd_bl | wr_sync | wr_bl | baa | adv | bls | ba |
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Value | - | - | - | b0 | b000 | b0 | b0 | - | - |
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Table
Field | t_rc | t_wc | t_ceoe | t_wp | t_pc | t_tr |
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Value | - | b0111 | - | b100 | - | - |
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Figure 2-17 shows an asynchronous write in multiplexed-mode. tWC is seven cycles. tWP is four cycles, and is extended by two cycles for the address phase of the transaction.
VPFBPFON |
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VPFBFVBQB>@ |
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VPFBDGYBQB |
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VPFBZHBQB | W:3 | |
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VPFBGDWDBRXWB>@ | $ | ' |
VPFBGDWDBHQB |
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Figure 2-17 Asynchronous write in multiplexed-mode
Asynchronous page mode read
Table 2-10 and Table 2-11 list the smc_opmode0_<0-3> and SRAM Register settings.
Table 2-10 Page read opmode chip register settings
Field | mw | rd_sync | rd_bl |
| wr_sync | wr_bl | baa | adv | bls | ba | |
Value | - | b0 | <page length> | - |
| - | - | - | - | b1 | |
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| Table | ||||||||
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| Field | t_rc |
| t_wc | t_ceoe | t_wp | t_pc | t_tr | |
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| Value | b0011 | - | b010 | - |
| b001 | - |
ARM DDI 0389B | Copyright © 2006 ARM Limited. All rights reserved. |