SMC Networks
PL241, AHB SRAM/NOR
manual
Glossary-6
Ad
Timing diagrams
AHB response signals
Smcuserconfig70
Smcmreset0n
Sram memory accesses
Direct commands
How to
Low-power interfaces
Using this manual
Big-endian 32-bit mode
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Glossary
Glossary-6
Copyright © 2006 ARM Limited. All rights reserved.
ARM DDI 0389B
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Contents
PrimeCell AHB SRAM/NOR Memory Controller PL241
Copyright 2006 ARM Limited. All rights reserved
PrimeCell AHB SRAM/NOR Memory Controller PL241
Technical Reference Manual
Contents
Chapter Programmer’s Model for Test
List of Tables
List of Tables
List of Figures
Figure A-1 AHB MC PL241 grouping of signals
Preface
Feedback on
Product revision status
Using this manual
About this manual
Intended audience
Bold
Conventions
Typographical
Timing diagrams
Signals
ARM publications
Numbering
Further reading
Feedback on this manual
Feedback
Feedback on this product
Introduction
SMC on
About the AHB MC
This section describes
AHB interface
AHB to APB bridge
Clock domains
Low-power interfaces
3 SMC
Supported devices
Intel W18 series NOR FLASH, for example 28f128W18td
Introduction Copyright 2006 ARM Limited. All rights reserved
Functional Overview
Functional description
This section is divided into
AHB clock domain
Smcmreset0n
Low-power interface
Static memory clock domain
Format on
SMC
Main blocks of the SMC are
Interrupts on
Format
SMC interface
APB slave interface
Memory manager
Pad interface
Interrupts
AHB fixed burst types
Functional operation
AHB interface operation
Broken bursts
Bufferable bit of the Hprot signal
Undefined length Incr bursts
Locked transfers
AHB response signals
Read after write hazard detection buffer
Registered Hwdata
Big-endian 32-bit mode
Removal of AHB error response logic
AHB to APB bridge operation
Clock domain operation
Ahbc memory map
1lists the static memory clocking options
Low-power interface operation
Static memory clocking options
Static memory clocking options
Where Domain is ahb or smc
An active output Domaincactive
Accepting requests
SMC states are as follows
SMC functional operation
Operating states
Clocking and resets
Clocking
Resets
Smcuserstatus70
Miscellaneous signals
Smcuserconfig70
Smcagtm0sync
Hazard handling
APB slave interface operation
Format block
Sram memory accesses
Memory burst length
Memory manager operation
Low-power operation
Chip configuration registers
11 Chip configuration registers
Software mechanism
Direct commands
Device pin mechanism
12 Device pin mechanism
13 Software mechanism
Memory interface operation
Sram timing tables and diagrams
Interrupts operation
Asynchronous read opmode chip register settings
Asynchronous read Sram cycles register settings
4and -5list the smcopmode00-3 and Sram Register settings
14 Asynchronous read
Asynchronous write Sram cycles register settings
6and -7list the smcopmode00-3 and Sram Register settings
Asynchronous write opmode chip register settings
10 Page read opmode chip register settings
8and -9list the smcopmode00-3 and Sram Register settings
10and -11list the smcopmode00-3 and Sram Register settings
13 Synchronous burst read Sram cycles register settings
12and -13list the smcopmode00-3 and Sram Register settings
12 Synchronous burst read opmode chip register settings
19 Synchronous burst read
14and -15list the smcopmode00-3 and Sram Register settings
20 Synchronous burst read in multiplexed-mode
17 Synchronous burst write Sram cycles register settings
16and -17list the smcopmode00-3 and Sram Register settings
16 Synchronous burst write opmode chip register settings
18and -19list the smcopmode00-3 and Sram Register settings
22 Synchronous burst write in multiplexed-mode
20and -21list the smcopmode00-3 and Sram Register settings
B0100 B0110 B001
TCEOE is only required if wait is asserted when oen goes LOW
TWC =
ARM DDI 0389B
Programmer’s Model
About the programmer’s model
2shows the SMC configuration register map
Register summary
Name Base offset Type Reset value Description
1lists the SMC Registers
Register summary
SMC Memory Controller Status Register at
Register descriptions
This section describes the SMC registers
2lists the register bit assignments
Bits Name Function
SMC Memory Interface Configuration Register at
3lists the register bit assignments
SMC Set Configuration Register at
Smcmemccfgset Register bit assignments
5lists the register bit assignments
SMC Clear Configuration Register at 0x100C
4lists the register bit assignments
Smcmemccfgclr Register bit assignments Bits Name Function
Smcdirectcmd Register bit assignments
SMC Direct Command Register at
6lists the register bit assignments
SMC Set Cycles Register at
Lists the register bit assignments
SMC Set Opmode Register at
12 smcsetopmode Register bit assignments
8lists the register bit assignments
Smcsetopmode Register bit assignments
Memory width mw field
Smcrefreshperiod0 Register bit assignments
SMC Refresh Period 0 Register at
SMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140
10lists the register bit assignments
SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144
11lists the register bit assignments
11 smcopmode Register bit assignments
SMC User Status Register at
12lists the register bit assignments
12 smcuserstatus Register bit assignments
13 lists the register bit assignments
SMC User Configuration Register at
13 smcuserconfig Register bit assignments
Bits Name Description
15 smcperiphid0 Register bit assignments Bits Name Function
Following section describe the smcperiphid Registers
SMC Peripheral Identification Register
16 smcperiphid1 Register bit assignments Bits Name Function
17 smcperiphid2 Register bit assignments Bits Name Function
SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC
19shows the register bit assignments
SMC PrimeCell Identification Register
These registers cannot be read in the Reset state
Following sections describe the smcpcellid Registers
20 smcpcellid0 Register bit assignments Bits Name Function
22 smcpcellid2 Register bit assignments Bits Name Function
23 smcpcellid3 Register bit assignments Bits Name Function
Programmer’s Model for Test
SMC integration test registers
Test registers are provided for integration testing
SMC Integration Configuration Register at 0x1E00
Lists the SMC integration test registers
Integration Inputs Register at 0x1E04
Smcintinputs Register bit assignments Bits Name Function
Integration Outputs Register at 0x1E08
State
Device Driver Requirements
Memory initialization
SMC and memory initialization sheet 1
SMC and memory initialization sheet 2
Where = denotes the appropriate chip select
SMC and memory initialization sheet 3
ARM DDI 0389B
Signal Descriptions
About the signals list
Where Ahbc = AHB Configuration signals
Name Type Source Description Destination
Clocks and resets
Table A-1lists the clock and reset signals
Where = 0 or C, where C = Configuration
AHB signals
Table A-2lists the AHB signals
Table A-2 AHB signals
SMC memory interface signals
Table A-3lists the SMC memory interface signals
Table A-4 SMC miscellaneous signals
SMC miscellaneous signals
Table A-4lists the SMC miscellaneous signals
Low-power interface
Table A-5lists the low-power interface signals
Table A-6 Configuration signal
Configuration signal
Table A-6lists the configuration signal
Name Source Description Type Destination
Scan chains
Table A-7lists the scan chain signals
Table A-7 Scan chain signals
ARM DDI 0389B
Advanced High-performance Bus AHB
Advanced Microcontroller Bus Architecture Amba
See also Little-endian memory
Advanced Peripheral Bus APB
Data bus
Incremented
An 8-bit data item
Multi-master operation
That event resource is Unpredictable
Divisible by four
See Unpredictable
Other purposes
Remapping
Has been completed
Written as 0 and read as
Reserved
Glossary-6
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