SMC Networks PL241, AHB SRAM/NOR manual Timing diagrams, Signals

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Preface

Note

Angle brackets can also enclose a permitted range of values. The example, <0-3>, shows that in name extensions, only one of the values 0, 1, 2, or 3 is valid.

Timing diagrams

The figure named Key to timing diagram conventions explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.

&ORFN

+,*+WR/2:

7UDQVLHQW +,*+/2:WR+,*+

%XVVWDEOH %XVWRKLJKLPSHGDQFH

%XVFKDQJH

+LJKLPSHGDQFHWRVWDEOHEXV

Key to timing diagram conventions

Signals

The signal conventions are:

Signal level	The level of an asserted signal depends on whether the signal is
	active-HIGH or active-LOW. Asserted means HIGH for
	active-HIGH signals and LOW for active-LOW signals.
Lower-case n	Denotes an active-LOW signal.
Prefix A	Denotes global Advanced eXtensible Interface (AXI) signals.
Prefix AR	Denotes AXI read address channel signals.
Prefix AW	Denotes AXI write address channel signals.

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Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

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Contents PrimeCell AHB SRAM/NOR Memory Controller PL241 PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference ManualCopyright 2006 ARM Limited. All rights reserved Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Preface Feedback onUsing this manual About this manualProduct revision status Intended audienceConventions TypographicalBold Timing diagrams SignalsNumbering Further readingARM publications Feedback Feedback on this productFeedback on this manual Introduction About the AHB MC This section describesSMC on AHB interface AHB to APB bridgeLow-power interfaces 3 SMCClock domains Supported devices Intel W18 series NOR FLASH, for example 28f128W18tdIntroduction Copyright 2006 ARM Limited. All rights reserved Functional Overview Functional description This section is divided intoSmcmreset0n Low-power interfaceAHB clock domain Static memory clock domainSMC Main blocks of the SMC areFormat on Interrupts onSMC interface APB slave interfaceFormat Memory managerPad interface InterruptsFunctional operation AHB interface operationAHB fixed burst types Bufferable bit of the Hprot signal Undefined length Incr burstsBroken bursts AHB response signals Read after write hazard detection bufferLocked transfers Big-endian 32-bit mode Removal of AHB error response logicRegistered Hwdata AHB to APB bridge operationClock domain operation Ahbc memory mapLow-power interface operation Static memory clocking options1lists the static memory clocking options Static memory clocking optionsWhere Domain is ahb or smc An active output DomaincactiveAccepting requests SMC functional operation Operating statesSMC states are as follows Clocking and resets ClockingResets Miscellaneous signals Smcuserconfig70Smcuserstatus70 Smcagtm0syncAPB slave interface operation Format blockHazard handling Sram memory accesses Memory burst length Low-power operation Chip configuration registersMemory manager operation 11 Chip configuration registers Direct commands Device pin mechanismSoftware mechanism 12 Device pin mechanism 13 Software mechanism Sram timing tables and diagrams Interrupts operationMemory interface operation Asynchronous read opmode chip register settings Asynchronous read Sram cycles register settings4and -5list the smcopmode00-3 and Sram Register settings 14 Asynchronous read6and -7list the smcopmode00-3 and Sram Register settings Asynchronous write opmode chip register settingsAsynchronous write Sram cycles register settings 8and -9list the smcopmode00-3 and Sram Register settings 10and -11list the smcopmode00-3 and Sram Register settings10 Page read opmode chip register settings 12and -13list the smcopmode00-3 and Sram Register settings 12 Synchronous burst read opmode chip register settings13 Synchronous burst read Sram cycles register settings 19 Synchronous burst read 14and -15list the smcopmode00-3 and Sram Register settings 20 Synchronous burst read in multiplexed-mode16and -17list the smcopmode00-3 and Sram Register settings 16 Synchronous burst write opmode chip register settings17 Synchronous burst write Sram cycles register settings 18and -19list the smcopmode00-3 and Sram Register settings 22 Synchronous burst write in multiplexed-mode20and -21list the smcopmode00-3 and Sram Register settings B0100 B0110 B001TCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model 2shows the SMC configuration register map Register summaryName Base offset Type Reset value Description 1lists the SMC RegistersRegister summary Register descriptions This section describes the SMC registersSMC Memory Controller Status Register at 2lists the register bit assignmentsSMC Memory Interface Configuration Register at 3lists the register bit assignmentsBits Name Function SMC Set Configuration Register at Smcmemccfgset Register bit assignmentsSMC Clear Configuration Register at 0x100C 4lists the register bit assignments5lists the register bit assignments Smcmemccfgclr Register bit assignments Bits Name FunctionSMC Direct Command Register at 6lists the register bit assignmentsSmcdirectcmd Register bit assignments SMC Set Cycles Register at Lists the register bit assignmentsSMC Set Opmode Register at 12 smcsetopmode Register bit assignments8lists the register bit assignments Smcsetopmode Register bit assignments Memory width mw fieldSMC Refresh Period 0 Register at SMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140Smcrefreshperiod0 Register bit assignments 10lists the register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x114411lists the register bit assignments SMC User Status Register at 12lists the register bit assignments11 smcopmode Register bit assignments 12 smcuserstatus Register bit assignmentsSMC User Configuration Register at 13 smcuserconfig Register bit assignments13 lists the register bit assignments Bits Name DescriptionFollowing section describe the smcperiphid Registers SMC Peripheral Identification Register15 smcperiphid0 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name FunctionSMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC 19shows the register bit assignmentsThese registers cannot be read in the Reset state Following sections describe the smcpcellid RegistersSMC PrimeCell Identification Register 20 smcpcellid0 Register bit assignments Bits Name Function22 smcpcellid2 Register bit assignments Bits Name Function 23 smcpcellid3 Register bit assignments Bits Name FunctionProgrammer’s Model for Test Test registers are provided for integration testing SMC Integration Configuration Register at 0x1E00SMC integration test registers Lists the SMC integration test registersIntegration Inputs Register at 0x1E04 Smcintinputs Register bit assignments Bits Name FunctionIntegration Outputs Register at 0x1E08 StateDevice Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 Where = denotes the appropriate chip select SMC and memory initialization sheet 3ARM DDI 0389B Signal Descriptions About the signals list Where Ahbc = AHB Configuration signalsClocks and resets Table A-1lists the clock and reset signalsName Type Source Description Destination AHB signals Table A-2lists the AHB signalsWhere = 0 or C, where C = Configuration Table A-2 AHB signalsSMC memory interface signals Table A-3lists the SMC memory interface signalsSMC miscellaneous signals Table A-4lists the SMC miscellaneous signalsTable A-4 SMC miscellaneous signals Low-power interface Table A-5lists the low-power interface signalsConfiguration signal Table A-6lists the configuration signalTable A-6 Configuration signal Name Source Description Type DestinationTable A-7lists the scan chain signals Table A-7 Scan chain signalsScan chains ARM DDI 0389B Advanced High-performance Bus AHB Advanced Microcontroller Bus Architecture AmbaSee also Little-endian memory Advanced Peripheral Bus APBIncremented An 8-bit data itemData bus Multi-master operationDivisible by four See UnpredictableThat event resource is Unpredictable Other purposesHas been completed Written as 0 and read asRemapping ReservedGlossary-6