SMC Networks AHB SRAM/NOR, PL241 APB slave interface operation, Format block, Hazard handling

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Functional Overview

smc_msync0

When HIGH, indicates smc_mclk0 is synchronous to smc_aclk. Otherwise they are asynchronous. Ensure that smc_msync0 is tied to the same value as smc_async0.

smc_rst_bypass

Use this signal for ATPG testing only. Tie it LOW for normal operation.

smc_use_ebi

When HIGH, indicates that the SMC must operate with a PrimeCell EBI.

See the ARM PrimeCell External Bus Interface (PL220) Technical

Reference Manual.

2.4.4APB slave interface operation

To enable a clean registered interface to the external infrastructure, the APB interface always adds a wait state for all reads and writes by driving pready LOW during the first cycle of the access phase.

In two instances, a delay of more than one wait state can be generated:

•when a direct command is received and there are outstanding commands that prevent a new command being stored in the command FIFO

•when an APB access is received and a previous direct command has not completed.

2.4.5Format block

This section describes:

•Hazard handling

•SRAM memory accesses on page 2-20.

Hazard handling

There are four types of hazard:

•Read After Read (RAR)

•Write After Write (WAW)

•Read After Write (RAW)

•Write After Read (WAR).

The AHB interface deals with RAW hazards. WAR hazards do not occur in the AHB.

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

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Contents PrimeCell AHB SRAM/NOR Memory Controller PL241 PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference ManualCopyright 2006 ARM Limited. All rights reserved Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Feedback on PrefaceIntended audience Using this manualAbout this manual Product revision statusConventions TypographicalBold Signals Timing diagramsNumbering Further readingARM publications Feedback Feedback on this productFeedback on this manual Introduction About the AHB MC This section describesSMC on AHB to APB bridge AHB interfaceLow-power interfaces 3 SMCClock domains Intel W18 series NOR FLASH, for example 28f128W18td Supported devicesIntroduction Copyright 2006 ARM Limited. All rights reserved Functional Overview This section is divided into Functional descriptionStatic memory clock domain Smcmreset0nLow-power interface AHB clock domainInterrupts on SMCMain blocks of the SMC are Format onMemory manager SMC interfaceAPB slave interface FormatInterrupts Pad interfaceFunctional operation AHB interface operationAHB fixed burst types Bufferable bit of the Hprot signal Undefined length Incr burstsBroken bursts AHB response signals Read after write hazard detection bufferLocked transfers AHB to APB bridge operation Big-endian 32-bit modeRemoval of AHB error response logic Registered HwdataAhbc memory map Clock domain operationStatic memory clocking options Low-power interface operationStatic memory clocking options 1lists the static memory clocking optionsAn active output Domaincactive Where Domain is ahb or smcAccepting requests SMC functional operation Operating statesSMC states are as follows Clocking Clocking and resetsResets Smcagtm0sync Miscellaneous signalsSmcuserconfig70 Smcuserstatus70APB slave interface operation Format blockHazard handling Sram memory accesses Memory burst length Low-power operation Chip configuration registersMemory manager operation 11 Chip configuration registers Direct commands Device pin mechanismSoftware mechanism 12 Device pin mechanism 13 Software mechanism Sram timing tables and diagrams Interrupts operationMemory interface operation Asynchronous read Sram cycles register settings Asynchronous read opmode chip register settings14 Asynchronous read 4and -5list the smcopmode00-3 and Sram Register settings6and -7list the smcopmode00-3 and Sram Register settings Asynchronous write opmode chip register settingsAsynchronous write Sram cycles register settings 8and -9list the smcopmode00-3 and Sram Register settings 10and -11list the smcopmode00-3 and Sram Register settings10 Page read opmode chip register settings 12and -13list the smcopmode00-3 and Sram Register settings 12 Synchronous burst read opmode chip register settings13 Synchronous burst read Sram cycles register settings 19 Synchronous burst read 20 Synchronous burst read in multiplexed-mode 14and -15list the smcopmode00-3 and Sram Register settings16and -17list the smcopmode00-3 and Sram Register settings 16 Synchronous burst write opmode chip register settings17 Synchronous burst write Sram cycles register settings 22 Synchronous burst write in multiplexed-mode 18and -19list the smcopmode00-3 and Sram Register settingsB0100 B0110 B001 20and -21list the smcopmode00-3 and Sram Register settingsTCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model Register summary 2shows the SMC configuration register map1lists the SMC Registers Name Base offset Type Reset value DescriptionRegister summary 2lists the register bit assignments Register descriptionsThis section describes the SMC registers SMC Memory Controller Status Register atSMC Memory Interface Configuration Register at 3lists the register bit assignmentsBits Name Function Smcmemccfgset Register bit assignments SMC Set Configuration Register atSmcmemccfgclr Register bit assignments Bits Name Function SMC Clear Configuration Register at 0x100C4lists the register bit assignments 5lists the register bit assignmentsSMC Direct Command Register at 6lists the register bit assignmentsSmcdirectcmd Register bit assignments Lists the register bit assignments SMC Set Cycles Register at12 smcsetopmode Register bit assignments SMC Set Opmode Register at8lists the register bit assignments Memory width mw field Smcsetopmode Register bit assignmentsSMC Refresh Period 0 Register at SMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140Smcrefreshperiod0 Register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 10lists the register bit assignments11lists the register bit assignments 12 smcuserstatus Register bit assignments SMC User Status Register at12lists the register bit assignments 11 smcopmode Register bit assignmentsBits Name Description SMC User Configuration Register at13 smcuserconfig Register bit assignments 13 lists the register bit assignmentsFollowing section describe the smcperiphid Registers SMC Peripheral Identification Register15 smcperiphid0 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function19shows the register bit assignments SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC20 smcpcellid0 Register bit assignments Bits Name Function These registers cannot be read in the Reset stateFollowing sections describe the smcpcellid Registers SMC PrimeCell Identification Register23 smcpcellid3 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name FunctionProgrammer’s Model for Test Lists the SMC integration test registers Test registers are provided for integration testingSMC Integration Configuration Register at 0x1E00 SMC integration test registersSmcintinputs Register bit assignments Bits Name Function Integration Inputs Register at 0x1E04State Integration Outputs Register at 0x1E08Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 SMC and memory initialization sheet 3 Where = denotes the appropriate chip selectARM DDI 0389B Signal Descriptions Where Ahbc = AHB Configuration signals About the signals listClocks and resets Table A-1lists the clock and reset signalsName Type Source Description Destination Table A-2 AHB signals AHB signalsTable A-2lists the AHB signals Where = 0 or C, where C = ConfigurationTable A-3lists the SMC memory interface signals SMC memory interface signalsSMC miscellaneous signals Table A-4lists the SMC miscellaneous signalsTable A-4 SMC miscellaneous signals Table A-5lists the low-power interface signals Low-power interfaceName Source Description Type Destination Configuration signalTable A-6lists the configuration signal Table A-6 Configuration signalTable A-7lists the scan chain signals Table A-7 Scan chain signalsScan chains ARM DDI 0389B Advanced Microcontroller Bus Architecture Amba Advanced High-performance Bus AHBAdvanced Peripheral Bus APB See also Little-endian memoryMulti-master operation IncrementedAn 8-bit data item Data busOther purposes Divisible by fourSee Unpredictable That event resource is UnpredictableReserved Has been completedWritten as 0 and read as RemappingGlossary-6