SMC Networks AHB SRAM/NOR, PL241 Read after write hazard detection buffer, AHB response signals

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Functional Overview

If transfers are described as non-bufferable then the bridge must wait for the write response to indicate that the transfer has been completed to memory. If numerous bufferable writes are performed, followed by a non-bufferable write, then the bridge must wait until it receives the write response associated with the final write.

Read after write hazard detection buffer

A RAW hazard detection buffer avoids potential RAW hazards. The protocol used internally to AHB MC does not perform memory coherency checks to catch Write After Read (WAR) or RAW hazards.

Because of the nature of the AHB protocol, WAR hazards never occur because the read must have completed before the write can be accepted.

Because the bridge permits writes to be buffered internally, there is a potential for a RAW hazard to occur. If you perform a bufferable write then it might not complete immediately. If a read to that same memory location is performed then both transfers can be in the queue and the internal memory controller can reorder these transactions for performance reasons so that the read occurs before the write. This means that the data read might be the value before the most recent write. The bridge has to detect these potential cases and stall the read transfer until any buffered writes that might cause a RAW hazard have been completed.

The bridge contains logic to monitor up to four outstanding write addresses. If an incoming read occurs to a 4KB region that has been written to, then it is stalled. If four bufferable writes occur then the AHB is stalled until a response is seen for the first of the four writes in the buffer.

AHB response signals

The interconnect used within the AHB MC contains many combinatorial paths that link different AHB input ports. To improve the synthesis timing, the AHB responses are registered to limit these paths to within the design.

Locked transfers

AHB MC supports locked transfers, within a 512MB region. This is because of the way the interconnect processes locked transfers. There is a significant performance penalty in using locked transfers. Transfers that are locked together wait for all other ports to complete any outstanding transfers before they can begin. While a locked sequence occurs to a specific 512MB memory region, all other access to that region is stalled. All locked writes are processed as non-bufferable writes and so have to wait for the appropriate write response before indicating their completion.

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

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Contents PrimeCell AHB SRAM/NOR Memory Controller PL241 Copyright 2006 ARM Limited. All rights reserved PrimeCell AHB SRAM/NOR Memory Controller PL241Technical Reference Manual Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Feedback on PrefaceAbout this manual Using this manualProduct revision status Intended audienceBold ConventionsTypographical Signals Timing diagramsARM publications NumberingFurther reading Feedback on this manual FeedbackFeedback on this product Introduction SMC on About the AHB MCThis section describes AHB to APB bridge AHB interfaceClock domains Low-power interfaces3 SMC Intel W18 series NOR FLASH, for example 28f128W18td Supported devicesIntroduction Copyright 2006 ARM Limited. All rights reserved Functional Overview This section is divided into Functional descriptionLow-power interface Smcmreset0nAHB clock domain Static memory clock domainMain blocks of the SMC are SMCFormat on Interrupts onAPB slave interface SMC interfaceFormat Memory managerInterrupts Pad interfaceAHB fixed burst types Functional operationAHB interface operation Broken bursts Bufferable bit of the Hprot signalUndefined length Incr bursts Locked transfers AHB response signalsRead after write hazard detection buffer Removal of AHB error response logic Big-endian 32-bit modeRegistered Hwdata AHB to APB bridge operationAhbc memory map Clock domain operationStatic memory clocking options Low-power interface operation1lists the static memory clocking options Static memory clocking optionsAn active output Domaincactive Where Domain is ahb or smcAccepting requests SMC states are as follows SMC functional operationOperating states Clocking Clocking and resetsResets Smcuserconfig70 Miscellaneous signalsSmcuserstatus70 Smcagtm0syncHazard handling APB slave interface operationFormat block Sram memory accesses Memory burst length Memory manager operation Low-power operationChip configuration registers 11 Chip configuration registers Software mechanism Direct commandsDevice pin mechanism 12 Device pin mechanism 13 Software mechanism Memory interface operation Sram timing tables and diagramsInterrupts operation Asynchronous read Sram cycles register settings Asynchronous read opmode chip register settings14 Asynchronous read 4and -5list the smcopmode00-3 and Sram Register settingsAsynchronous write Sram cycles register settings 6and -7list the smcopmode00-3 and Sram Register settingsAsynchronous write opmode chip register settings 10 Page read opmode chip register settings 8and -9list the smcopmode00-3 and Sram Register settings10and -11list the smcopmode00-3 and Sram Register settings 13 Synchronous burst read Sram cycles register settings 12and -13list the smcopmode00-3 and Sram Register settings12 Synchronous burst read opmode chip register settings 19 Synchronous burst read 20 Synchronous burst read in multiplexed-mode 14and -15list the smcopmode00-3 and Sram Register settings17 Synchronous burst write Sram cycles register settings 16and -17list the smcopmode00-3 and Sram Register settings16 Synchronous burst write opmode chip register settings 22 Synchronous burst write in multiplexed-mode 18and -19list the smcopmode00-3 and Sram Register settingsB0100 B0110 B001 20and -21list the smcopmode00-3 and Sram Register settingsTCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model Register summary 2shows the SMC configuration register map1lists the SMC Registers Name Base offset Type Reset value DescriptionRegister summary This section describes the SMC registers Register descriptionsSMC Memory Controller Status Register at 2lists the register bit assignmentsBits Name Function SMC Memory Interface Configuration Register at3lists the register bit assignments Smcmemccfgset Register bit assignments SMC Set Configuration Register at4lists the register bit assignments SMC Clear Configuration Register at 0x100C5lists the register bit assignments Smcmemccfgclr Register bit assignments Bits Name FunctionSmcdirectcmd Register bit assignments SMC Direct Command Register at6lists the register bit assignments Lists the register bit assignments SMC Set Cycles Register at12 smcsetopmode Register bit assignments SMC Set Opmode Register at8lists the register bit assignments Memory width mw field Smcsetopmode Register bit assignmentsSmcrefreshperiod0 Register bit assignments SMC Refresh Period 0 Register atSMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140 SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 10lists the register bit assignments11lists the register bit assignments 12lists the register bit assignments SMC User Status Register at11 smcopmode Register bit assignments 12 smcuserstatus Register bit assignments13 smcuserconfig Register bit assignments SMC User Configuration Register at13 lists the register bit assignments Bits Name Description15 smcperiphid0 Register bit assignments Bits Name Function Following section describe the smcperiphid RegistersSMC Peripheral Identification Register 17 smcperiphid2 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function19shows the register bit assignments SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFCFollowing sections describe the smcpcellid Registers These registers cannot be read in the Reset stateSMC PrimeCell Identification Register 20 smcpcellid0 Register bit assignments Bits Name Function23 smcpcellid3 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name FunctionProgrammer’s Model for Test SMC Integration Configuration Register at 0x1E00 Test registers are provided for integration testingSMC integration test registers Lists the SMC integration test registersSmcintinputs Register bit assignments Bits Name Function Integration Inputs Register at 0x1E04State Integration Outputs Register at 0x1E08Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 SMC and memory initialization sheet 3 Where = denotes the appropriate chip selectARM DDI 0389B Signal Descriptions Where Ahbc = AHB Configuration signals About the signals listName Type Source Description Destination Clocks and resetsTable A-1lists the clock and reset signals Table A-2lists the AHB signals AHB signalsWhere = 0 or C, where C = Configuration Table A-2 AHB signalsTable A-3lists the SMC memory interface signals SMC memory interface signalsTable A-4 SMC miscellaneous signals SMC miscellaneous signalsTable A-4lists the SMC miscellaneous signals Table A-5lists the low-power interface signals Low-power interfaceTable A-6lists the configuration signal Configuration signalTable A-6 Configuration signal Name Source Description Type DestinationScan chains Table A-7lists the scan chain signalsTable A-7 Scan chain signals ARM DDI 0389B Advanced Microcontroller Bus Architecture Amba Advanced High-performance Bus AHBAdvanced Peripheral Bus APB See also Little-endian memoryAn 8-bit data item IncrementedData bus Multi-master operationSee Unpredictable Divisible by fourThat event resource is Unpredictable Other purposesWritten as 0 and read as Has been completedRemapping ReservedGlossary-6
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