
Programmer’s Model
Table 3-11 lists the register bit assignments.
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Bits | Name | Function | |
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[31:24] | address_match | Returns the value of this | |
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| determine the chip that is selected. | |
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[23:16] | address_mask | Returns the value of this | |
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| chip that must be selected. A logic 1 indicates the bit is used for comparison. | |
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[15:13] | burst_align | These bits determine whether memory bursts are split on memory burst boundaries: | |
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| 000 | = bursts can cross any address boundary |
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| 001 | = burst split on memory burst boundary, that is, 32 beats for continuous |
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| 010 | = burst split on 64 beat boundary |
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| 011 | = burst split on 128 beat boundary |
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| 100 | = burst split on 256 beat boundary |
others = reserved.
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| Note |
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| For asynchronous transfers: | ||||
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| • | the AHB MC always aligns read bursts to the memory burst boundary, when | |||
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| rd_sync = 0 | |||
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| • | the AHB MC always aligns write bursts to the memory burst boundary, when | |||
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| wr_sync = 0. | |||
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[12] | bls | This bit affects the assertion of the | ||||
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| b0 = bls timing equals chip select timing. This is the default setting. | ||||
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| b1 = bls timing equals smc_we_n_0 timing. This setting is used for | ||||
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| no Byte Lane Strobe inputs. In this case, the smc_bls_n_0[3:0] output of the memory | ||||
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| controller is connected to the smc_we_n_0 memory input. | ||||
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[11] | adv | The memory uses the address advance signal smc_adv_n_0 when set. | ||||
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[10] | baa | The memory uses the burst advance signal smc_baa_n_0 when set. | ||||
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[9:7] | wr_bl | Determines the memory burst length for writes: | ||||
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| b000 | = 1 beat | |||
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| b001 | = 4 beats | |||
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| b010 | = 8 beats | |||
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| b011 | = 16 beats | |||
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| b100 | = 32 beats | |||
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| b101 | = continuous |
ARM DDI 0389B | Copyright © 2006 ARM Limited. All rights reserved. |