Cypress CY7C0430BV Maximum Frequency, Clock Cycle Time, Clock High Time, Address Set-up Time

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CY7C0430BV

CY7C0430CV

Switching Characteristics Over the Industrial Operating Range

[6]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C0430BV and CY7C0430CV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–133

 

–100

 

Parameter

 

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

Min.

 

Max.

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

fMAX2[7]

 

Maximum Frequency

 

 

133

 

 

100

MHz

tCYC2[7]

 

Clock Cycle Time

7.5

 

 

10

 

 

ns

tCH2

 

Clock HIGH Time

3

 

 

4

 

 

ns

tCL2

 

Clock LOW Time

3

 

 

4

 

 

ns

tR

 

Clock Rise Time

 

 

2

 

 

3

ns

tF

 

Clock Fall Time

 

 

2

 

 

3

ns

tSA

 

Address Set-up Time

2.3

 

 

3

 

 

ns

tHA

 

Address Hold Time

0.7

 

 

0.7

 

 

ns

tSC

 

Chip Enable Set-up Time

2.3

 

 

3

 

 

ns

tHC

 

Chip Enable Hold Time

0.7

 

 

0.7

 

 

ns

tSW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

Set-up Time

2.3

 

 

3

 

 

ns

tHW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

Hold Time

0.7

 

 

0.7

 

 

ns

tSD

 

Input Data Set-up Time

2.3

 

 

3

 

 

ns

tHD

 

Input Data Hold Time

0.7

 

 

0.7

 

 

ns

tSB

 

Byte Set-up Time

2.3

 

 

3

 

 

ns

tHB

 

Byte Hold Time

0.7

 

 

0.7

 

 

ns

tSCLD

 

 

 

 

 

 

 

 

 

Set-up Time

2.3

 

 

3

 

 

ns

CNTLD

 

 

 

 

tHCLD

 

 

 

 

 

 

 

 

 

Hold Time

0.7

 

 

0.7

 

 

ns

CNTLD

 

 

 

 

tSCINC

 

 

 

 

 

 

 

 

 

 

 

Set-up Time

2.3

 

 

3

 

 

ns

CNTINC

 

 

 

 

tHCINC

 

 

 

 

 

 

 

 

 

 

 

Hold Time

0.7

 

 

0.7

 

 

ns

CNTINC

 

 

 

 

tSCRST

 

 

 

 

 

 

 

 

 

 

 

 

Set-up Time

2.3

 

 

3

 

 

ns

CNTRST

 

 

 

 

tHCRST

 

 

 

 

 

 

 

 

 

 

 

 

Hold Time

0.7

 

 

0.7

 

 

ns

CNTRST

 

 

 

 

tSCRD

 

 

 

 

 

 

 

 

 

Set-up Time

2.3

 

 

3

 

 

ns

CNTRD

 

 

 

 

tHCRD

 

 

 

 

 

 

 

 

 

Hold Time

0.7

 

 

0.7

 

 

ns

CNTRD

 

 

 

 

tSMLD

 

 

 

 

 

 

 

Set-up Time

2.3

 

 

3

 

 

ns

MKLD

 

 

 

 

tHMLD

 

 

 

 

 

 

 

Hold Time

0.7

 

 

0.7

 

 

ns

MKLD

 

 

 

 

tSMRD

 

 

 

 

 

 

 

Set-up Time

2.3

 

 

3

 

 

ns

MKRD

 

 

 

 

tHMRD

 

 

 

 

 

 

 

Hold Time

0.7

 

 

0.7

 

 

ns

MKRD

 

 

 

 

tOE

 

Output Enable to Data Valid

 

 

6.5

 

 

8

ns

tOLZ[8]

 

 

 

to Low-Z

1

 

 

1

 

 

ns

OE

 

 

 

 

tOHZ[8]

 

 

 

to High-Z

1

 

6

1

 

7

ns

OE

tCD2

 

Clock to Data Valid

 

 

4.2

 

 

5

ns

tCA2

 

Clock to Counter Address Readback Valid

 

 

4.7

 

 

5

ns

tCM2

 

Clock to Mask Register Readback Valid

 

 

4.7

 

 

5

ns

tDC

 

Data Output Hold After Clock HIGH

1

 

 

1

 

 

ns

tCKHZ[9]

 

Clock HIGH to Output High-Z

1

 

4.8

1

 

6.8

ns

Notes:

6.If data is simultaneously written and read to the same address location and tCCS is violated, the data read from the address, as well as the subsequent data remaining in the address is undefined.

7.fMAX2 for commercial is 135 MHz. tCYC2 Min. for commercial is 7.4 ns.

8.This parameter is guaranteed by design, but it is not production tested.

9.Valid for both address and data outputs.

Document #: 38-06027 Rev. *B

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Contents QuadPort DSE Family Applications FeaturesCypress Semiconductor Corporation Processor Processed Data Path Functional DescriptionProcessor Pre-processed Data Path Queue #1Top Level Logic Block Diagram Port 1 Operation-control Logic Blocks2Port 1 Operation-Control Logic Block Diagram Address Readback is independent of CEsPin Configuration Ball Grid Array BGA Top ViewCY7C0430CV Unit Selection GuidePin Definitions Port DescriptionMask Register Readback Input . When asserted LOW Counter Interrupt Flag Output . Flag is asserted LOWOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings CapacitanceNormal Load Three-State DelayAC Test Load TAP LoadOutput Enable to Data Valid Chip Enable Set-up TimeChip Enable Hold Time Maximum FrequencyJtag Timing and Switching Waveforms Switching Waveforms Master Reset10Data OUT CLKAddress LatencyAddress B1 Bank Select Read 17Read-to-Write-to-Read OE = Read No Operation WriteCntld Cntinc Read-to-Write-to-Read OE Controlled19, 20, 21Read with Address Counter Advance23 DataoutWrite External Write with Write with Address Counter Advance 24Address Internal Counter HoldData Data OUT Counter Reset 21, 26Counter Write Read Reset Address Address nCntrd Internal Load and Read Address Counter28Load Read Data with Counter External Address Internal Mkrd Mask Internal Value Load and Read Mask RegisterMkld Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Counter Interrupt 37, 38 Mailbox Interrupt Timing40, 41, 42, 43Mode Operation OperationInterrupt Operation Example Master ResetInterrupts Port FunctionCntrd Mkrd Address Counter Control OperationsCntinc = Cntld = Cntrst = CLK Counter-Mask Register Test Mode Select Disabling the Jtag FeatureTest Access Port TAP-Test Clock TCK Performing a TAP ResetIdentification ID Register Non-Debug Mode Go-NoGoTAP Instruction Set Boundary Scan Cells BSC Debug ModeMbist Control States P4IO17-9TAP Controller State Diagram FSM53 EXIT2-IR UPDATE-DR UPDATE-IRMbist Debug Register MDR 391 JTAG/BIST TAP Controller Block DiagramMUX Bist TAP ControllerPlaces the bypass register BYR between TDI and TDO Scan Registers Sizes Register Name Bit SizeInstruction Identification Codes Description Between TDI and TDOMbist Control Register MCR MCR10 Mode CLKP4 Boundary Scan Order Cell # Signal Name Bump Ball IDCE0 CLKP3CLKP2 Ordering Information Package Diagram Lead Pbga 27 x 27 x 2.33 mm BG272SZV Issue Orig. Description of Change DateDocument History FSG
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