Cypress CY7C0430CV, CY7C0430BV manual Jtag Timing and Switching Waveforms

Page 11

CY7C0430BV

CY7C0430CV

Switching Characteristics Over the Industrial Operating Range

 

(continued)[6]

 

 

 

 

 

 

 

 

 

 

 

 

CY7C0430BV and CY7C0430CV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–133

–100

 

 

Parameter

 

 

 

 

 

Description

 

 

 

 

 

 

 

Unit

 

 

 

 

 

 

Min.

 

Max.

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

tCKLZ[9]

Clock HIGH to Output Low-Z

1

 

 

1

 

 

ns

tSINT

Clock to

 

 

Set Time

1

 

7.5

1

 

10

ns

INT

tRINT

Clock to

 

 

Reset Time

1

 

7.5

1

 

10

ns

INT

tSCINT

Clock to

 

 

 

 

Set Time

1

 

7.5

1

 

10

ns

CNTINT

tRCINT

Clock to

 

 

 

 

Reset Time

1

 

7.5

1

 

10

ns

CNTINT

Master Reset Timing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRS

Master Reset Pulse Width

7.5

 

 

10

 

 

ns

tRSR

Master Reset Recovery Time

7.5

 

 

10

 

 

ns

tROF

Master Reset to Output Flags Reset Time

 

 

 

6.5

 

 

8

ns

Port to Port Delays

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCCS[6]

Clock to Clock Set-up Time (time required after a write

6.5

 

 

9

 

 

ns

 

before you can read the same address location)

 

 

 

 

 

 

 

 

JTAG Timing and Switching Waveforms

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Quadport DSE Family

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–133/–100

 

 

Parameter

 

 

 

 

 

Description

 

 

 

 

 

Unit

 

 

 

 

 

 

 

Min.

Max.

 

fJTAG

Maximum JTAG TAP Controller Frequency

 

 

 

 

10

 

MHz

tTCYC

TCK Clock Cycle Time

 

 

100

 

 

 

ns

tTH

TCK Clock High Time

 

 

40

 

 

 

ns

tTL

TCK Clock Low Time

 

 

40

 

 

 

ns

tTMSS

TMS Set-up to TCK Clock Rise

 

 

20

 

 

 

ns

tTMSH

TMS Hold After TCK Clock Rise

 

 

20

 

 

 

ns

tTDIS

TDI Set-up to TCK Clock Rise

 

 

20

 

 

 

ns

tTDIH

TDI Hold after TCK Clock Rise

 

 

20

 

 

 

ns

tTDOV

TCK Clock Low to TDO Valid

 

 

 

 

20

 

ns

tTDOX

TCK Clock Low to TDO Invalid

 

 

0

 

 

 

ns

fBIST

Maximum CLKBIST Frequency

 

 

 

 

50

 

MHz

tBH

CLKBIST High Time

 

 

6

 

 

 

ns

tBL

CLKBIST Low Time

 

 

6

 

 

 

ns

Document #: 38-06027 Rev. *B

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Contents Cypress Semiconductor Corporation FeaturesQuadPort DSE Family Applications Queue #1 Functional DescriptionProcessor Pre-processed Data Path Processor Processed Data PathPort 1 Operation-control Logic Blocks2 Top Level Logic Block DiagramAddress Readback is independent of CEs Port 1 Operation-Control Logic Block DiagramBall Grid Array BGA Top View Pin ConfigurationPort Description Selection GuidePin Definitions CY7C0430CV UnitCounter Interrupt Flag Output . Flag is asserted LOW Mask Register Readback Input . When asserted LOWCapacitance Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeTAP Load Three-State DelayAC Test Load Normal LoadMaximum Frequency Chip Enable Set-up TimeChip Enable Hold Time Output Enable to Data ValidJtag Timing and Switching Waveforms Master Reset10 Switching WaveformsLatency CLKAddress Data OUTRead No Operation Write Bank Select Read 17Read-to-Write-to-Read OE = Address B1Dataout Read-to-Write-to-Read OE Controlled19, 20, 21Read with Address Counter Advance23 Cntld CntincCounter Hold Write with Address Counter Advance 24Address Internal Write External Write withAddress n Counter Reset 21, 26Counter Write Read Reset Address Data Data OUTLoad Read Data with Counter External Address Internal Load and Read Address Counter28Cntrd Internal Load Read Mask Register Value Load and Read Mask RegisterMkld Mkrd Mask Internal ValuePort 1 Write to Port 2 Read34, 35 Mailbox Interrupt Timing40, 41, 42, 43 Counter Interrupt 37, 38Operation Mode OperationPort Function Master ResetInterrupts Interrupt Operation ExampleCntinc = Cntld = Cntrst = CLK Address Counter Control OperationsCntrd Mkrd Counter-Mask Register Performing a TAP Reset Disabling the Jtag FeatureTest Access Port TAP-Test Clock TCK Test Mode SelectTAP Instruction Set Non-Debug Mode Go-NoGoIdentification ID Register P4IO17-9 Debug ModeMbist Control States Boundary Scan Cells BSCEXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram FSM53Bist TAP Controller JTAG/BIST TAP Controller Block DiagramMUX Mbist Debug Register MDR 391Between TDI and TDO Scan Registers Sizes Register Name Bit SizeInstruction Identification Codes Description Places the bypass register BYR between TDI and TDOMbist Control Register MCR MCR10 Mode CLKP3 Boundary Scan Order Cell # Signal Name Bump Ball IDCE0 CLKP4CLKP2 Ordering Information Lead Pbga 27 x 27 x 2.33 mm BG272 Package DiagramFSG Issue Orig. Description of Change DateDocument History SZV