Cypress CY7C0430CV manual Master Reset, Interrupts, Interrupt Operation Example, Port Function

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CY7C0430BV

CY7C0430CV

Master Reset

The QuadPort DSE device undergoes a complete reset by taking its Master Reset (MRST) input LOW. The Master Reset input can switch asynchronously to the clocks. A Master Reset initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). A Master Reset also forces the Mailbox Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH, resets the BIST controller, and takes all registered control signals to a deselected read state.[50] A Master Reset must be performed on the QuadPort DSE device after power-up.

Interrupts

The upper four memory locations may be used for message passing and permit communications between ports. Table 3 shows the interrupt operation for all ports. For the 1-Mb QuadPort DSE device, the highest memory location FFFF is

Table 3. Interrupt Operation Example

the mailbox for Port 1, FFFE is the mailbox for Port 2, FFFD is the mailbox for Port 3, and FFFC is the mailbox for Port 4. Table 3 shows that in order to set Port 1 INTP1 flag, a write by any other port to address FFFF will assert INTP1 LOW. A read of FFFF location by Port 1 will reset INTP1 HIGH. When one port writes to the other port’s mailbox, the Interrupt flag (INT) of the port that the mailbox belongs to is asserted LOW. The Interrupt is reset when the owner (port) of the mailbox reads the contents of the mailbox. The interrupt flag is set in a flow-through mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-through mode (i.e., it follows the clock edge of the reading port).

Each port can read the other port’s mailbox without resetting the interrupt. If an application does not require message passing, INT pins should be treated as no-connect and should be left floating. When two ports or more write to the same mailbox at the same time INT will be asserted but the contents of the mailbox are not guaranteed to be valid.

 

 

 

 

 

 

 

 

Port 1

 

 

Port 2

 

 

Port 3

 

 

Port 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Function

A0P1–15P1

 

INT

P1

A0P2–15P2

 

INT

P2

A0P3–15P3

 

INT

P3

A0P4–15P4

 

INT

P4

Set Port 1

 

 

 

P1 Flag

X

 

L

FFFF

 

X

FFFF

 

X

FFFF

 

X

INT

Reset Port 1

 

 

 

 

P1 Flag

FFFF

 

H

X

 

X

X

 

X

X

 

X

INT

Set Port 2

 

 

 

 

P2 Flag

FFFE

 

X

X

 

L

FFFE

 

X

FFFE

 

X

INT

Reset Port 2

 

 

 

 

P2 Flag

X

 

X

FFFE

 

H

X

 

X

X

 

X

INT

Set Port 3

 

 

 

 

P3 Flag

FFFD

 

X

FFFD

 

X

X

 

L

FFFD

 

X

INT

Reset Port 3

 

 

 

 

P3 Flag

X

 

X

X

 

X

FFFD

 

H

X

 

X

INT

Set Port 4

 

 

 

 

P4 Flag

FFFC

 

X

FFFC

 

X

FFFC

 

X

X

 

L

INT

Reset Port 4

 

 

 

 

P4 Flag

X

 

X

X

 

X

X

 

X

FFFC

 

H

INT

Note:

50.During Master Reset the control signals will be set to a deselected read state: CE0I = LBI = UBI = R/WI = MKLDI = MKRDI = CNTRDI = CNTRSTI = CNTLDI = CNTINCI = VIH; CE1I = VIL. The “I” suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals.

Document #: 38-06027 Rev. *B

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Contents Cypress Semiconductor Corporation FeaturesQuadPort DSE Family Applications Queue #1 Functional DescriptionProcessor Pre-processed Data Path Processor Processed Data PathPort 1 Operation-control Logic Blocks2 Top Level Logic Block DiagramAddress Readback is independent of CEs Port 1 Operation-Control Logic Block DiagramBall Grid Array BGA Top View Pin ConfigurationPort Description Selection GuidePin Definitions CY7C0430CV UnitCounter Interrupt Flag Output . Flag is asserted LOW Mask Register Readback Input . When asserted LOWCapacitance Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeTAP Load Three-State DelayAC Test Load Normal LoadMaximum Frequency Chip Enable Set-up TimeChip Enable Hold Time Output Enable to Data ValidJtag Timing and Switching Waveforms Master Reset10 Switching WaveformsLatency CLKAddress Data OUTRead No Operation Write Bank Select Read 17Read-to-Write-to-Read OE = Address B1Dataout Read-to-Write-to-Read OE Controlled19, 20, 21Read with Address Counter Advance23 Cntld CntincCounter Hold Write with Address Counter Advance 24Address Internal Write External Write withAddress n Counter Reset 21, 26Counter Write Read Reset Address Data Data OUTLoad Read Data with Counter External Address Internal Load and Read Address Counter28Cntrd Internal Load Read Mask Register Value Load and Read Mask RegisterMkld Mkrd Mask Internal ValuePort 1 Write to Port 2 Read34, 35 Mailbox Interrupt Timing40, 41, 42, 43 Counter Interrupt 37, 38Operation Mode OperationPort Function Master ResetInterrupts Interrupt Operation ExampleCntinc = Cntld = Cntrst = CLK Address Counter Control OperationsCntrd Mkrd Counter-Mask Register Performing a TAP Reset Disabling the Jtag FeatureTest Access Port TAP-Test Clock TCK Test Mode SelectTAP Instruction Set Non-Debug Mode Go-NoGoIdentification ID Register P4IO17-9 Debug ModeMbist Control States Boundary Scan Cells BSCEXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram FSM53Bist TAP Controller JTAG/BIST TAP Controller Block DiagramMUX Mbist Debug Register MDR 391Between TDI and TDO Scan Registers Sizes Register Name Bit SizeInstruction Identification Codes Description Places the bypass register BYR between TDI and TDOMbist Control Register MCR MCR10 Mode CLKP3 Boundary Scan Order Cell # Signal Name Bump Ball IDCE0 CLKP4CLKP2 Ordering Information Lead Pbga 27 x 27 x 2.33 mm BG272 Package DiagramFSG Issue Orig. Description of Change DateDocument History SZV
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