Cypress CY7C0430BV Functional Description, Processor Pre-processed Data Path, Queue #1, Queue #2

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CY7C0430BV

CY7C0430CV

PORT 1

PORT 2

PORT 3

PORT 4

DATA PATH AGGREGATOR

Processor 1

Pre-processed DATA Path

QuadPort DSE Family

Processor 2

Processed DATA Path

DATA PATH MANAGER FOR

PARALLEL PACKET PROCESSING

Queue #1

PORT 1

PORT 3

Queue #2

PORT 2

PORT 4

DATA CLASSIFICATION ENGINE

Functional Description

The Quadport Datapath Switching Element (DSE) family offers four ports that may be clocked at independent frequencies from one another. Each port can read or write up to 133 MHz[1], giving the device up to 10 Gb/s of data throughput. The device is 1-Mb (64K × 18) in density. Simultaneous reads are allowed for accesses to the same address location; however, simulta- neous reading and writing to the same address is not allowed. Any port can write to a certain location while other ports are reading that location simultaneously, if the timing spec for port to port delay (tCCS) is met. The result of writing to the same location by more than one port at the same time is undefined.

Data is registered for decreased cycle time. Clock to data valid tCD2 = 4.2 ns. Each port contains a burst counter on the input

address register. After externally loading the counter with the initial address the counter will self-increment the address inter- nally (more details to follow). The internal write pulse width is independent of the duration of the R/W input signal. The internal write pulse is self-timed to allow the shortest possible cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle is required with chip enables asserted to reactivate the outputs.

The CY7C0430BV and CY7C0430CV (64K × 18 device) supports burst contains for simple array partitioning. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst

Document #: 38-06027 Rev. *B

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Contents Cypress Semiconductor Corporation FeaturesQuadPort DSE Family Applications Processor Processed Data Path Functional DescriptionProcessor Pre-processed Data Path Queue #1Top Level Logic Block Diagram Port 1 Operation-control Logic Blocks2Port 1 Operation-Control Logic Block Diagram Address Readback is independent of CEsPin Configuration Ball Grid Array BGA Top ViewCY7C0430CV Unit Selection GuidePin Definitions Port DescriptionMask Register Readback Input . When asserted LOW Counter Interrupt Flag Output . Flag is asserted LOWOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings CapacitanceNormal Load Three-State DelayAC Test Load TAP LoadOutput Enable to Data Valid Chip Enable Set-up TimeChip Enable Hold Time Maximum FrequencyJtag Timing and Switching Waveforms Switching Waveforms Master Reset10Data OUT CLKAddress LatencyAddress B1 Bank Select Read 17Read-to-Write-to-Read OE = Read No Operation WriteCntld Cntinc Read-to-Write-to-Read OE Controlled19, 20, 21Read with Address Counter Advance23 DataoutWrite External Write with Write with Address Counter Advance 24Address Internal Counter HoldData Data OUT Counter Reset 21, 26Counter Write Read Reset Address Address nLoad Read Data with Counter External Address Internal Load and Read Address Counter28Cntrd Internal Mkrd Mask Internal Value Load and Read Mask RegisterMkld Load Read Mask Register ValuePort 1 Write to Port 2 Read34, 35 Counter Interrupt 37, 38 Mailbox Interrupt Timing40, 41, 42, 43Mode Operation OperationInterrupt Operation Example Master ResetInterrupts Port FunctionCntinc = Cntld = Cntrst = CLK Address Counter Control OperationsCntrd Mkrd Counter-Mask Register Test Mode Select Disabling the Jtag FeatureTest Access Port TAP-Test Clock TCK Performing a TAP ResetTAP Instruction Set Non-Debug Mode Go-NoGoIdentification ID Register Boundary Scan Cells BSC Debug ModeMbist Control States P4IO17-9TAP Controller State Diagram FSM53 EXIT2-IR UPDATE-DR UPDATE-IRMbist Debug Register MDR 391 JTAG/BIST TAP Controller Block DiagramMUX Bist TAP ControllerPlaces the bypass register BYR between TDI and TDO Scan Registers Sizes Register Name Bit SizeInstruction Identification Codes Description Between TDI and TDOMbist Control Register MCR MCR10 Mode CLKP4 Boundary Scan Order Cell # Signal Name Bump Ball IDCE0 CLKP3CLKP2 Ordering Information Package Diagram Lead Pbga 27 x 27 x 2.33 mm BG272SZV Issue Orig. Description of Change DateDocument History FSG